Datasheet

Section 21 List of Registers
Rev. 4.00 Mar. 15, 2006 Page 416 of 556
REJ09B0026-0400
21.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Register Name
Abbre-
viation Bit No Address
Module
Name
Data
Bus
Width
Access
State
   H'F000 to
H'F5FF
  
Master control register MCR 8 H'F600 TinyCAN 8 4
General status register GSR 8 H'F601 TinyCAN 8 4
Bit configuration register 1 BCR1 8 H'F602 TinyCAN 8 4
Bit configuration register 0 BCR0 8 H'F603 TinyCAN 8 4
Mailbox configuration register MBCR 8 H'F604 TinyCAN 8 4
TinyCAN module control register TCMR 8 H'F605 TinyCAN 8 4
Transmit pending register TXPR 8 H'F606 TinyCAN 8 4
Transmit pending cancel register TXCR 8 H'F608 TinyCAN 8 4
Transmit acknowledge register TXACK 8 H'F60A TinyCAN 8 4
Abort acknowledge register ABACK 8 H'F60C TinyCAN 8 4
Receive complete register RXPR 8 H'F60E TinyCAN 8 4
Remote request register RFPR 8 H'F610 TinyCAN 8 4
TinyCAN interrupt register 1 TCIRR1 8 H'F612 TinyCAN 8 4
TinyCAN interrupt register 0 TCIRR0 8 H'F613 TinyCAN 8 4
Mailbox interrupt mask register MBIMR 8 H'F614 TinyCAN 8 4
TinyCAN interrupt mask register 1 TCIMR1 8 H'F616 TinyCAN 8 4
TinyCAN interrupt mask register 0 TCIMR0 8 H'F617 TinyCAN 8 4
Receive error counter REC 8 H'F618 TinyCAN 8 4
Transmit error counter TEC 8 H'F619 TinyCAN 8 4
Test control register TCR 8 H'F61A TinyCAN 8 4
Unread message status register UMSR 8 H'F61B TinyCAN 8 4
Message control 0 [0] MC0[0] 8 H'F620 TinyCAN 8 4