Datasheet

Rev. 4.00 Mar. 15, 2006 Page 551 of 556
REJ09B0026-0400
Item Page Revision (See Manual for Details)
Figure 12.45 Example of Output
Disable Timing of Timer Z by
External Trigger
230 Amended
WKP4
TOER
Timer Z
output pin
Timer Z output I/O port
N H'FF
φ
Amended
Bit Bit Name Description
4 TCSRWE Timer Control/Status Register WD
Write Enable
The WDON and WRST bits can
be written when the TCSRWE bit
is set to 1.
When writing data to this bit, the
value for bit 5 must be 0.
13.2.1 Timer Control/Status
Register WD (TCSRWD)
246
16.5 Usage Note 378 Added
18.3.1 A/D Data Registers A to D
(ADDRA to ADDRD)
394 Amended
…. The temporary register contents are transferred
from the ADDR when the upper byte data is read.
Therefore, byte access to ADDR should be done by
reading the upper byte first then the lower one. Word
access is also possible. ADDR is initialized to H'0000.
Figure 19.1 Block Diagram of
Power-On Reset Circuit and Low-
Voltage Detection Circuit
404 Amended
RES
C
RES