To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/36064 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series H8/36064GF HD64F36064G Rev.2.00 2005.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/36064 Group is a single-chip microcomputer made up of the high-speed H8/300H CPU as its core, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36064 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Notes: When using an on-chip emulator (E7, E8) for H8/36064 program development and debugging, the following restrictions must be noted . 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 4. Area H'F780 to H'FB7F must on no account be accessed. 5.
Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note TM Single Power Supply F-ZTAT On-Board Programming Rev. 2.00 Sep.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Assignment ...................................................................................
3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) ...................................................................... 49 3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 49 3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 51 3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 51 Reset Exception Handling........
6.2 6.3 6.4 6.5 Mode Transitions and States of LSI..................................................................................... 75 6.2.1 Sleep Mode ............................................................................................................. 76 6.2.2 Standby Mode ......................................................................................................... 77 6.2.3 Subsleep Mode..............................................................................................
9.3 9.4 9.5 9.6 9.7 9.8 9.2.3 Port Mode Register 3 (PMR3) .............................................................................. 104 9.2.4 Pin Functions ........................................................................................................ 105 Port 3.................................................................................................................................. 107 9.3.1 Port Control Register 3 (PCR3) ..........................................................
Section 11 Timer V............................................................................................133 11.1 Features.............................................................................................................................. 133 11.2 Input/Output Pins ............................................................................................................... 135 11.3 Register Descriptions ........................................................................................
12.4.6 Reset Synchronous PWM Mode........................................................................... 193 12.4.7 Complementary PWM Mode................................................................................ 197 12.4.8 Buffer Operation................................................................................................... 208 12.4.9 Timer Z Output Timing ........................................................................................ 216 12.5 Interrupts.....................
15.5 15.6 15.7 15.8 15.4.3 Data Transmission ................................................................................................ 258 15.4.4 Serial Data Reception ........................................................................................... 260 Operation in Clocked Synchronous Mode ......................................................................... 264 15.5.1 Clock..............................................................................................................
16.4.7 Noise Canceler...................................................................................................... 308 16.4.8 Example of Use..................................................................................................... 308 16.5 Interrupt Requests .............................................................................................................. 313 16.6 Bit Synchronous Circuit..........................................................................................
Section 20 List of Registers ...............................................................................343 20.1 Register Addresses (Address Order).................................................................................. 344 20.2 Register Bits....................................................................................................................... 350 20.3 Registers States in Each Operating Mode ..........................................................................
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Figures Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 3 Figure 1.2 Pin Assignment (FP-64A, FP-64E) ............................................................................... 4 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 10 Figure 2.2 CPU Registers ...................................................
Figure 5.7 Example of Incorrect Board Design ............................................................................ 68 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 75 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 ROM Flash Memory Block Configuration............................................................................ 80 Programming/Erasing Flowchart Example in User Program Mode.
Figure 12.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode ............................................................................................................. 160 Figure 12.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) ........ 174 Figure 12.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits))............. 174 Figure 12.7 Example of Counter Operation Setting Procedure ..................................................
Figure 12.39 Example of Compare Match Timing for Buffer Operation ................................... 211 Figure 12.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) ...................................................... 212 Figure 12.41 Input Capture Timing of Buffer Operation............................................................ 213 Figure 12.42 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 214 Figure 12.
Figure 15.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 258 Figure 15.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 259 Figure 15.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 260 Figure 15.
Figure 16.18 Figure 16.19 Figure 16.20 Figure 16.21 Sample Flowchart for Master Receive Mode ........................................................ 310 Sample Flowchart for Slave Transmit Mode......................................................... 311 Sample Flowchart for Slave Receive Mode .......................................................... 312 Timing of Bit Synchronous Circuit ....................................................................... 314 Section 17 Figure 17.1 Figure 17.
Figure B.10 Port 3 Block Diagram (P37 to P30) ........................................................................ 420 Figure B.11 Port 5 Block Diagram (P57, P56) ........................................................................... 421 Figure B.12 Port5 Block Diagram (P55) .................................................................................... 422 Figure B.13 Port 5 Block Diagram (P54 to P50) ........................................................................ 423 Figure B.
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Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 18 Table 2.2 Data Transfer Instructions....................................................................................... 19 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.4 Table 7.5 Table 7.6 Reprogram Data Computation Table ...................................................................... 90 Additional-Program Data Computation Table ........................................................ 90 Programming Time ................................................................................................. 90 Section 10 Timer B1 Table 10.1 Pin Configuration..................................................................................................
Table 16.4 Time for Monitoring SCL..................................................................................... 314 Section 17 A/D Converter Table 17.1 Pin Configuration.................................................................................................. 291 Table 17.2 Analog Input Channels and Corresponding ADDR Registers .............................. 292 Table 17.3 A/D Conversion Time (Single Mode)...................................................................
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Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory Model Product Classification Flash memory version TM (F-ZTAT version) H8/36064GF On-Chip Power-On Reset and Low-Voltage Detecting Circuit Version ROM RAM Remarks HD64F36064G 32 kbytes 2 kbytes Under development Note: F-ZTATTM is a trademark of Renesas Technology Corp. • General I/O ports I/O pins: 45 I/O pins, including 8 large current ports (IOL = 20 mA, @VOL = 1.
Section 1 Overview System clock generator NMI TEST RES Port 6 Port 7 Port 1 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 Port 2 IIC2 14-bit PWM SCI3_2 Timer Z Watchdog timer Timer V Port 8 SCI3 Timer B1 P87 P86 P85 A/D converter Data bus (upper) Address bus Port B AVCC P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 ROM PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB
Section 1 Overview P62/FTIOC0 P61/FTIOB0 NMI P60/FTIOA0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 P85 P86 P87 P20/SCK3 P21/RXD P22/TXD P23 Pin Assignment P70/SCK3_2 1.
Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. FP-64A Type Symbol FP-64E I/O Functions Power source pins VCC 12 Input Power supply pin. Connect this pin to the system power supply. VSS 9 Input Ground pin. Connect this pin to the system power supply (0V). AVCC 3 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. VCL 6 Input Internal step-down power supply pin.
Section 1 Overview Pin No.
Section 1 Overview Pin No. FP-64A Type Symbol FP-64E I/O Functions I/O ports PB7 to PB0 1, 2, 59 to 64 Input 8-bit input port. P17 to P14, P12 to P10 51 to 54, 23 to 25 I/O 7-bit I/O port. P24 to P20 31, 44 to 47 I/O 5-bit I/O port.
Section 1 Overview Rev. 2.00 Sep.
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU • Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0 to 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 2.00 Sep.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD, SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.4.
Section 2 CPU (3) Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to Appendix A.
Section 2 CPU (2) Register Indirect@Ern The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.
Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF (6) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly.
Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For details on the data bus width and number of access states of each register, refer to section 20.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.
Section 2 CPU The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. Read Count clock Timer counter Reload Write Timer load register Internal data bus Figure 2.
Section 2 CPU • After executing BSET instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 0 1 0 0 0 0 0 1 • Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5.
Section 2 CPU • BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0). • After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5 The work area (RAM0) value is written to PDR5.
Section 2 CPU • After executing BCLR instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 1 1 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 • Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5.
Section 2 CPU • After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5 The work area (RAM0) value is written to PCR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 0 Rev. 2.00 Sep.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
Section 3 Exception Handling Vector Number Vector Address Priority Transmit data empty Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop condition detection 24 H'0030, H'0031 High A/D converter A/D conversion end 25 H'0032, H'0033 Timer Z Compare match/input capture A0 to D0 Timer Z overflow 26 H'0034, H'0035 Compare match/input capture A1 to D1 Timer Z overflow Timer Z underflow 27 H'0036, H'0037 Timer B1 Timer B1 overflow 29 H'003A, H'003B SCI3_2 Rec
Section 3 Exception Handling 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of the NMI and IRQ3 to IRQ0 pins. Bit Initial Bit Name Value R/W Description 7 NMIEG R/W NMI Edge Select 0 0: Falling edge of NMI pin input is detected 1: Rising edge of NMI pin input is detected 6 to 4 All 1 Reserved These bits are always read as 1.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5 to WKP0 pins. Bit Initial Bit Name Value R/W Description 7, 6 All 1 Reserved 5 WPEG5 0 R/W WKP5 Edge Select These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts and external pin interrupts. Bit Initial Bit Name Value R/W Description 7 IENDT R/W Direct Transfer Interrupt Enable 0 When this bit is set to 1, direct transition interrupt requests are enabled. 6 0 Reserved This bit is always read as 0. 5 IENWP 0 R/W Wakeup Interrupt Enable This bit is an enable bit, which is common to the WKP5 to WKP0 pins.
Section 3 Exception Handling 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Bit Initial Bit Name Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 IENTB1 0 R/W 4 to 0 All 1 Timer B1 Interrupt Enable When this bit is set to 1, timer B1 overflow interrupt requests are enabled. Reserved These bits are always read as 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI3 is cleared by writing 0 2 IRRI2 0 R/W IRQ2 Interrupt Request Flag [Setting condition] When IRQ2 pin is designated for interrupt input and the designated signal edge is detected.
Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Bit Initial Bit Name Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 IRRTB1 0 R/W Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter value overflows [Clearing condition] When IRRTB1 is cleared by writing 0 4 to 0 All 1 Reserved These bits are always read as 1. 3.2.
Section 3 Exception Handling Bit Initial Bit Name Value R/W Description 3 IWPF3 R/W WKP3 Interrupt Request Flag 0 [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0.
Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. The reset exception handling sequence is shown in figure 3.1. For details, refer to section 18, Power-On Reset and Low-Voltage Detection Circuits. The reset exception handling sequence is as follows: 1. Set the I bit in the condition code register (CCR) to 1.
Section 3 Exception Handling (3) WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to the WKP5 to WKP0 pins. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of the WPEG5 to WPEG0 bits in IEGR2.
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt.
Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR*3 SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
(2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions The address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Initial Bit Name Value R/W Description 1 0 DCMP1 DCMP0 R/W R/W Data Compare Condition Select 1 and 0 These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus 0 0 [Legend] X: Don't care.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Initial Bit Name Value R/W Description 7 ABIF R/W Address Break Interrupt Flag 0 [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF = 1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit readable/writable registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH for byte access.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators A clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and a system clock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
Section 5 Clock Pulse Generators 5.1.1 Connecting Crystal Resonator Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 5.1 should be used. C1 OSC 1 C2 OSC 2 C1 = C 2 = 12 pF ±20% Figure 5.3 Typical Connection to Crystal Resonator LS RS CS OSC 1 OSC 2 C0 Figure 5.
Section 5 Clock Pulse Generators 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 OSC2 C1 = 30 pF ±10% C2 = 30 pF ±10% Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 External Clock Input Method Connect an external clock signal to the OSC1 pin and leave the OSC2 pin open. Figure 5.6 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%. OSC1 OSC 2 External clock input Open Figure 5.
Section 5 Clock Pulse Generators 5.2 Prescalers 5.2.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has five modes of operation after a reset. These include a normal active mode and three power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Initial Bit Name Value R/W Description 7 SSBY R/W Software Standby 0 This bit selects the transition mode after the execution of the SLEEP instruction. 0: A transition is made to sleep mode 1: A transition is made to standby mode For details, see table 6.2.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time Bit Name Operating Frequency STS2 STS1 STS0 Waiting Time 0 0 1 1 0 1 20 MHz 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 8,192 states 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8 0 32,768 states 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1 0 131,072 states 6.6 8.2 13.1 16.4 32.8 65.5 131.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Initial Bit Name Value R/W Description 7 SMSEL R/W Sleep Mode Selection 0 This bit selects the transition mode after the execution of the SLEEP instruction, as well as the SSBY bit in SYSCR1. For details, see table 6.2. 6 0 Reserved This bit is always read as 0.
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Initial Bit Name Value R/W Description 7 Reserved 0 This bit is always read as 0. 6 MSTIIC 0 R/W IIC2 Module Standby IIC2 enters standby mode when this bit is set to 1. 5 MSTS3 0 R/W SCI3 Module Standby 4 MSTAD 0 R/W A/D Converter Module Standby SCI3 enters standby mode when this bit is set to 1.
Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Initial Bit Name Value R/W Description 7 MSTS3_2 0 R/W SCI3_2 Module Standby SCI3_2 enters standby mode when this bit is set to 1. 6, 5 All 0 Reserved These bits are always read as 0. 4 MSTTB1 0 R/W 3, 2 All 0 Timer B1 Module Standby Timer B1 enters standby mode when this bit is set to 1.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition from active mode to active mode changes the operating frequency.
Section 6 Power-Down Modes Note: * Table 6.3 When a state transition is made while the SMSEL bit is 1, the timer V, SCI3, SCI3_2, and A/D converter are reset, and all registers are set to their initial values. To use these functions after entering active mode, reset the registers.
Section 6 Power-Down Modes 6.2.2 Standby Mode In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt.
Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in active mode. The operating frequency can be changed by making a transition directly from active mode to active mode.
Section 7 ROM Section 7 ROM The features of the 32-kbyte (4 kbytes are used for E7 or E8 control program area) flash memory built into the flash memory (F-ZTAT) version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 28 kbytes × 1 block. To erase the entire flash memory, each block must be erased in turn.
Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 kbyte × 4 blocks, and 28 kbytes × 1 block. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing.
Section 7 ROM Bit Initial Bit Name Value R/W Description 2 PV R/W Program-Verify 0 When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory changes to program mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Initial Bit Name Value R/W Description 7 to 5 Reserved All 0 These bits are always read as 0. 4 EB4 0 R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased.
Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. The SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3.
Section 7 ROM Boot Mode Operation Host Operation Processing Contents Communication Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 to 20 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Comments Table 7.
Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes No Yes SWE bit ← 0 SWE bit
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.
Section 8 RAM Section 8 RAM This LSI has an on-chip 2-kbyte high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version Note: * H8/36064GF RAM Size RAM Address 2 kbytes H'F780 to H'FF7F* When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed. RAM0200A_000020030600 Rev. 2.00 Sep.
Section 8 RAM Rev. 2.00 Sep.
Section 9 I/O Ports Section 9 I/O Ports This LSI has 45 general I/O ports and eight general input-only ports. Port 6 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Initial Bit Name Value R/W Description 7 IRQ3 R/W This bit selects the function of pin P17/IRQ3/TRGV. 0 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W This bit selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W This bit selects the function of pin P15/IRQ1/TMIB1.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Initial Bit Name Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Initial Bit Name Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pullup MOS of P17 to P14 and P12 to P10 pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
Section 9 I/O Ports • P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Pin Function 0 P16 input pin 1 P16 output pin X IRQ2 input pin Setting value 0 1 [Legend] X: Don't care. • P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function 0 P15 input pin 1 P15 output pin X IRQ1 input/TMIB1 input pin Setting value 0 1 [Legend] X: Don't care.
Section 9 I/O Ports • P12 pin Register PCR1 Bit Name PCR12 Pin Function Setting value 0 P12 input pin 1 P12 output pin • P11/PWM pin Register PMR1 PCR1 Bit Name PWM PCR11 Pin Function 0 P11 input pin 1 P11 output pin X PWM output pin Setting value 0 1 [Legend] X: Don't care. • P10 pin Register PCR1 Bit Name PCR10 Setting value 0 1 Pin Function P10 input pin P10 output pin Rev. 2.00 Sep.
Section 9 I/O Ports 9.2 Port 2 Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins for both uses. P24 P23 P22/TXD Port 2 P21/RXD P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. • Port control register 2 (PCR2) • Port data register 2 (PDR2) • Port mode register 3 (PMR3) 9.2.
Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Initial Bit Name Value R/W Description 7 to 5 Reserved All 1 These bits are always read as 1. 4 P24 0 R/W PDR2 stores output data for port 2 pins. 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read.
Section 9 I/O Ports 9.2.4 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function 0 P21 input pin 1 P21 output pin X RXD input pin Setting Value 0 1 [Legend] X: Don't care. • P20/SCK3 pin Register Bit Name SCR3 CKE1 Setting Value 0 SMR PCR2 CKE0 COM PCR20 Pin Function 0 0 0 P20 input pin 1 P20 output pin 0 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin [Legend] X: Don't care. Rev. 2.00 Sep.
Section 9 I/O Ports 9.3 Port 3 Port 3 is a general I/O port. Each pin of the port 3 is shown in figure 9.3. P37 P36 P35 P34 Port 3 P33 P32 P31 P30 Figure 9.3 Port 3 Pin Configuration Port 3 has the following registers. • Port control register 3 (PCR3) • Port data register 3 (PDR3) 9.3.1 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Section 9 I/O Ports 9.3.2 Port Data Register 3 (PDR3) PDR3 is a general I/O port data register of port 3. Bit Initial Bit Name Value R/W Description 7 P37 0 R/W PDR3 stores output data for port 3 pins. 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W If PDR3 is read while PCR3 bits are set to 1, the value stored in PDR3 is read. If PDR3 is read while PCR3 bits are cleared to 0, the pin states are read regardless of the value stored in PDR3.
Section 9 I/O Ports • P35 pin Register PCR3 Bit Name PCR35 Setting Value 0 1 Pin Function P35 input pin P35 output pin • P34 pin Register PCR3 Bit Name PCR34 Setting Value 0 1 Pin Function P34 input pin P34 output pin • P33 pin Register PCR3 Bit Name PCR33 Setting Value 0 1 Pin Function P33 input pin P33 output pin • P32 pin Register PCR3 Bit Name PCR32 Setting Value 0 1 Pin Function P32 input pin P32 output pin • P31 pin Register PCR3 Bit Name PCR31 Setting Value 0 1 Pin Funct
Section 9 I/O Ports • P30 pin Register PCR3 Bit Name PCR30 Pin Function Setting Value 0 P30 input pin 1 9.4 P30 output pin Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, and a wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register setting of PMR5 has priority for functions of the pins for both uses. P57/SCL P56/SDA P55/WKP5/ADTRG Port 5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 9.
Section 9 I/O Ports 9.4.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Initial Bit Name Value R/W Description 7 POF57 0 R/W 6 POF56 0 R/W When set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 5 WKP5 0 R/W This bit selects the function of pin P55/WKP5/ADTRG.
Section 9 I/O Ports 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Initial Bit Name Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.4.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Initial Bit Name Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W 2 PUCR52 0 R/W 1 PUCR51 0 R/W 0 PUCR50 0 R/W 9.4.5 Pin Functions Only bits for which PCR5 is cleared are valid.
Section 9 I/O Ports • P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Pin Function 0 P56 input pin 1 P56 output pin X SDA I/O pin Setting Value 0 1 [Legend] X: Don't care. SDA performs the NMOS open-drain output, which enables direct bus drive. • P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin Setting Value 0 1 [Legend] X: Don't care.
Section 9 I/O Ports • P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function 0 P53 input pin 1 P53 output pin X WKP3 input pin Setting Value 0 1 [Legend] X: Don't care. • P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function 0 P52 input pin 1 P52 output pin X WKP2 input pin Setting Value 0 1 [Legend] X: Don't care.
Section 9 I/O Ports • P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function 0 P50 input pin 1 P50 output pin X WKP0 input pin Setting Value 0 1 [Legend] X: Don't care. 9.5 Port 6 Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z has priority for functions of the pins for both uses.
Section 9 I/O Ports 9.5.1 Port Control Register 6 (PCR6) PCR6 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 6. Bit Initial Bit Name Value R/W Description 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W When each of the port 6 pins P67 to P60 functions as a general I/O port, setting a PCR6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P67/FTIOD1 pin Register TOER TFCR Bit Name ED1 Setting Value 1 0 TPMR TIORC1 CMD1, CMD0 PWMD1 IOD2 to IOD0 PCR67 Pin Function 00 0 000 or 1XX 0 P67 input/FTIOD1 input pin 1 P67 output pin X FTIOD1 output pin 00 0 001 or 01X 1 XXX Other than X 00 XXX PCR6 [Legend] X: Don't care.
Section 9 I/O Ports • P65/FTIOB1 pin Register TOER TFCR TPMR TIORA1 Bit Name EB1 CMD1, CMD0 PWMB1 IOB2 to IOB0 PCR65 Pin Function 00 0 000 or 1XX 0 P65 input/FTIOB1 input pin 1 P65 output pin X FTIOB1 output pin Setting Value 1 0 00 0 001 or 01X 1 XXX Other than X 00 XXX PCR6 [Legend] X: Don't care.
Section 9 I/O Ports • P63/FTIOD0 pin Register TOER TFCR TPMR TIORC0 Bit Name ED0 CMD1, CMD0 PWMD0 IOD2 to IOD0 PCR63 Pin Function 00 0 000 or 1XX 0 P63 input/FTIOD0 input pin 1 P63 output pin X FTIOD0 output pin Setting Value 1 0 00 0 001 or 01X 1 XXX Other than X 00 XXX PCR6 [Legend] X: Don't care.
Section 9 I/O Ports • P61/FTIOB0 pin Register TOER TFCR TPMR TIORA0 PCR6 Bit Name EB0 CMD1, CMD0 PWMB0 IOB2 to IOB0 PCR61 Pin Function Setting Value 00 0 P61 input/FTIOB0 input pin 1 P61 output pin X FTIOB0 output pin 1 0 00 0 000 or 1XX 0 001 or 01X 1 XXX Other than 00 X XXX [Legend] X: Don't care.
Section 9 I/O Ports 9.6 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings of the timer V, PMR1, and SCI3_2 have priority for functions of the pins for both uses. P76/TMOV P75/TMCIV P74/TMRIV Port 7 P72/TXD_2 P71/RXD_2 P70/SCK3_2 Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.6.
Section 9 I/O Ports 9.6.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Initial Bit Name Value R/W Description 7 1 Stores output data for port 7 pins. 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 are read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. 3 1 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W 9.
Section 9 I/O Ports • P75/TMCIV pin Register PCR7 Bit Name PCR75 Pin Function Setting Value 0 P75 input/TMCIV input pin 1 P75 output/TMCIV input pin • P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin • P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Pin Function Setting Value 0 0 P72 input pin 1 P72 output pin X TXD_2 output pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P70/SCK3_2 pin Register SCR3_2 SMR2 PCR7 Bit Name CKE1 CKE0 COM PCR70 Pin Function Setting Value 0 0 0 0 P70 input pin 1 P70 output pin 0 0 1 X SCK3_2 output pin 0 1 X X SCK3_2 output pin 1 X X X SCK3_2 input pin [Legend] X: Don't care. 9.7 Port 8 Port 8 is a general I/O port. Each pin of the port 8 is shown in figure 9.7. P87 Port 8 P86 P85 Figure 9.7 Port 8 Pin Configuration Port 8 has the following registers.
Section 9 I/O Ports 9.7.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Bit Bit Name Initial Value R/W Description 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W When each of the port 8 pins P87 to P85 functions as a general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 to 0 Reserved 9.7.
Section 9 I/O Ports • P86 pin Register PCR8 Bit Name PCR86 Pin Function Setting Value 0 P86 input pin 1 P86 output pin • P85 pin Register PCR8 Bit Name PCR85 Pin Function Setting Value 0 P85 input pin 1 P85 output pin 9.8 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.
Section 9 I/O Ports 9.8.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B. Bit Initial Bit Name Value 7 PB7 6 PB6 5 R/W Description R R The input value of each pin is read by reading this register. PB5 R 4 PB4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB0 R Rev. 2.00 Sep. 23, 2005 Page 128 of 444 REJ09B0068-0200 However, if a port B pin is designated as an analog input channel by ADCSR in A/D converter, 0 is read.
Section 10 Timer B1 Section 10 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1. 10.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or an external clock (can be used to count external events). • An interrupt is generated when the counter overflows.
Section 10 Timer B1 10.3 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 10.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Bit Initial Bit Name Value R/W Description 7 TMB17 R/W Auto-reload function select 0 0: Interval timer function selected 1: Auto-reload function selected 6 to 3 All 1 Reserved These bits are always read as 1.
Section 10 Timer B1 10.3.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by the TMB12 to TMB10 bits in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 10.3.
Section 10 Timer B1 10.4.2 Auto-Reload Timer Operation Setting the TMB17 bit in TMB1 to 1 causes the timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes the timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value.
Section 11 Timer V Section 11 Timer V The timer V is an 8-bit timer based on an 8-bit counter. The timer V counts external events. Compare-match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.
Section 11 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Output control TCSRV Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B
Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 11.3 Register Descriptions The time V has the following registers.
Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit readable/writable registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, the CMFA flag in TCSRV is set to 1. If the CMIEA bit in TCRV0 is also set to 1, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
Section 11 Timer V 11.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Initial Bit Name Value R/W Description 7 CMIEB R/W Compare Match Interrupt Enable B 0 When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. 6 CMIEA 0 R/W Compare Match Interrupt Enable A When this bit is set to 1, interrupt request from the CMFA bit in TCSRV is enabled.
Section 11 Timer V Table 11.
Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
Section 11 Timer V Bit Initial Bit Name Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
Section 11 Timer V 11.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Initial Bit Name Value R/W Description 7 to 5 All 1 Reserved 4 TVEG1 0 R/W TRGV Input Edge Select 3 TVEG0 0 R/W These bits select the TRGV input edge. These bits are always read as 1.
Section 11 Timer V 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. 2.
Section 11 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 11.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 11.4 OVF Set Timing Rev. 2.00 Sep.
Section 11 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 11.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 11.7 Clear Timing by Compare Match Rev. 2.00 Sep.
Section 11 Timer V φ TMRIV (External counter reset input pin) TCNTV reset signal N–1 TCNTV N H'00 Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set the CCLR1 and CCLR0 bits in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set the CCLR1 and CCLR0 bits in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set the OS3 to OS0 bits in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. 2.
Section 11 Timer V TCORA write cycle by CPU T2 T1 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. 2.00 Sep.
Section 12 Timer Z Section 12 Timer Z The timer Z has a 16-bit timer with two channels. Figures 12.1, 12.2, and 12.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, refer to table 12.1. 12.
Section 12 Timer Z • Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 12.
Section 12 Timer Z ITMZ0 FTIOA0 ITMZ1 FTIOB0 FTIOC0 FTIOD0 FTIOA1 Control logic FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8 ADTRG TSTR Channel 0 timer Channel 1 timer TMDR TPMR TFCR TOER TOCR Module data bus [Legend] TSTR: TMDR: TPMR: TFCR: TOER: TOCR: ADTRG: ITMZ0: ITMZ1: Timer start register (8 bits) Timer mode register (8 bits) Timer PWM mode register (8 bits) Timer function control register (8 bits) Timer output master enable register (8 bits) Timer output control register (8 bits) A/D conve
Section 12 Timer Z FTIOA0 FTIOB0 φ, φ/2, φ/4, φ/8 FTIOC0 Clock select FTIOD0 Control logic ITMZ0 POCR_0 TIER_0 TSR_0 TIORC_0 TIORA_0 TCR_0 GRD_0 GRC_0 GRB_0 GRA_0 TCNT_0 Comparator Module data bus [Legend] TCNT_0 : TCR_0 : GRA_0, GRB_0: GRC_0, GRD_0 : TIORA_0 : TIORC_0 : TSR_0 : TIER_0 : POCR_0 : ITMZ0 : Timer counter_0 (16 bits) General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits × 4) Timer control register_0 (8 bits) Timer I/O control register A_0
Section 12 Timer Z FTIOA1 FTIOB1 φ, φ/2, φ/4, φ/8 FTIOC1 Clock select FTIOD1 Control logic ITMZ1 POCR_1 TIER_1 TSR_1 TIORC_1 TIORA_1 TCR_1 GRD_1 GRC_1 GRB_1 GRA_1 TCNT_1 Comparator Module data bus [Legend] TCNT_1 : GRA_1, GRB_1: GRC_1, GRD_1 : TCR_1 : TIORA_1 : TIORC_1 : TSR_1 : TIER_1 : POCR_1 : ITMZ1 : Timer counter_1 (16 bits) General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers: 16 bits × 4) Timer control register_1 (8 bits) Timer I/O control register A_1
Section 12 Timer Z 12.2 Input/Output Pins Table 12.2 summarizes the timer Z pins. Table 12.
Section 12 Timer Z 12.3 Register Descriptions The timer Z has the following registers.
Section 12 Timer Z • General register C_1 (GRC_1) • General register D_1 (GRD_1) 12.3.1 Timer Start Register (TSTR) TSTR selects the operation/stop for the TCNT counter. Bit Initial Bit Name Value R/W Description 7 to 2 Reserved All 1 These bits are always read as 1, and cannot be modified. 1 STR1 0 R/W Channel 1 Counter Start 0: TCNT_1 halts counting 1: TCNT_1 starts counting 0 STR0 0 R/W Channel 0 Counter Start 0: TCNT_0 halts counting 1: TCNT_0 starts counting Rev. 2.00 Sep.
Section 12 Timer Z 12.3.2 Timer Mode Register (TMDR) TMDR selects buffer operation settings and synchronized operation.
Section 12 Timer Z 12.3.3 Timer PWM Mode Register (TPMR) TPMR sets the pin to enter PWM mode. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1, and cannot be modified.
Section 12 Timer Z 12.3.4 Timer Function Control Register (TFCR) TFCR selects the settings and output levels for each operating mode. Bit Initial Bit Name Value R/W 7 1 Description Reserved This bit is always read as 1.
Section 12 Timer Z Bit Initial Bit Name Value R/W Description 1 CMD1 0 R/W Combination Mode 1 and 0 0 CMD0 0 R/W 00: Channel 0 and channel 1 operate normally 01: Channel 0 and channel 1 are used together to operate in reset synchronous PWM mode 10: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the trough) 11: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the crest) Note: When reset synchronous PWM
Section 12 Timer Z 12.3.5 Timer Output Master Enable Register (TOER) TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output for timer Z.
Section 12 Timer Z Bit Initial Bit Name Value R/W Description 2 EC0 R/W Master Enable C0 1 0: FTIOC0 pin output is enabled according to the TPMR, TFCR, and TIORC_0 settings 1: FTIOC0 pin output is disabled regardless of the TPMR, TFCR, and TIORC_0 settings (FTIOC0 pin is operated as an I/O port).
Section 12 Timer Z 12.3.6 Timer Output Control Register (TOCR) TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and complementary PWM mode.
Section 12 Timer Z 12.3.7 Timer Counter (TCNT) The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT counters are 16-bit readable/writable registers that increment/decrement according to input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1 increment/decrement in complementary PWM mode, while they only increment in other modes.
Section 12 Timer Z 12.3.9 Timer Control Register (TCR) The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Section 12 Timer Z Bit Initial Bit Name value R/W Description 2 TPSC2 0 R/W Time Prescaler 2 to 0 1 TPSC1 0 R/W 000: Internal clock: count by φ 0 TPSC0 0 R/W 001: Internal clock: count by φ/2 010: Internal clock: count by φ/4 011: Internal clock: count by φ/8 1XX: External clock: count by FTIOA0 (TCLK) pin input Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match. When GR functions as input capture, TCNT is cleared by input capture. 2.
Section 12 Timer Z 12.3.10 Timer I/O Control Register (TIORA and TIORC) The TIOR registers control the general registers (GR). Timer Z has four TIOR registers (TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid. (1) TIORA TIORA selects whether GRA or GRB is used as an output compare register or an input capture register.
Section 12 Timer Z Bit Initial Bit Name value R/W Description 2 IOA2 0 R/W I/O Control A2 to A0 1 IOA1 0 R/W GRA is an output compare register: 0 IOA0 0 R/W 000: Disables pin output by compare match 001: 0 output by GRA compare match 010: 1 output by GRA compare match 011: Toggle output by GRA compare match GRA is an input capture register: 100: Input capture to GRA at the rising edge 101: Input capture to GRA at the falling edge 11X: Input capture to GRA at both rising and falling edges
Section 12 Timer Z (2) TIORC TIORC selects whether GRC or GRD is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TIORC also selects the function of FTIOC or FTIOD pin. Bit Bit Name Initial value R/W Description 7 1 Reserved This bit is always read as 1.
Section 12 Timer Z 12.3.11 Timer Status Register (TSR) TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers, one for each channel. Bit Initial Bit Name value R/W Description 7, 6 Reserved All 1 These bits are always read as 1.
Section 12 Timer Z Bit Initial Bit Name value R/W Description 2 IMFC R/W Input Capture/Compare Match Flag C 0 [Setting conditions] • When TCNT = GRC and GRC is functioning as output compare register • When TCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register [Clearing condition] • 1 IMFB 0 R/W When 0 is written to IMFC after reading IMFC = 1 Input Capture/Compare Match Flag B [Setting conditions] • When TCNT = GRB and GRB is functionin
Section 12 Timer Z 12.3.12 Timer Interrupt Enable Register (TIER) TIER enables or disables interrupt requests for overflow or GR compare match/input capture. Timer Z has two TIER registers, one for each channel. Bit Initial Bit Name value R/W Description 7 to 5 All 1 Reserved 4 OVIE 0 R/W Overflow Interrupt Enable These bits are always read as 1.
Section 12 Timer Z 12.3.13 PWM Mode Output Level Control Register (POCR) POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each channel. Bit Initial Bit Name value R/W Description 7 to 3 All 1 Reserved 2 POLD 0 R/W PWM Mode Output Level Control D These bits are always read as 1.
Section 12 Timer Z 12.3.14 Interface with CPU 1. 16-bit register TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 12.5 shows an example of accessing the 16-bit registers. Internal data bus H C P L Module data bus Bus interface U TCNTH TCNTL Figure 12.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) 2.
Section 12 Timer Z 12.4 Operation 12.4.1 Counter Operation When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Figure 12.7 shows an example of the counter operation setting procedure.
Section 12 Timer Z 1. Free-running count operation and periodic count operation Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt.
Section 12 Timer Z Figure 12.9 illustrates periodic counter operation. TCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 12.9 Periodic Counter Operation 2. TCNT count timing A. Internal clock operation A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock can be selected by bits TPSC2 to TPSC0 in TCR. Figure 12.10 illustrates this timing. φ Internal clock TCNT input TCNT N-1 N N+1 Figure 12.
Section 12 Timer Z B. External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 12.
Section 12 Timer Z 12.4.2 Waveform Output by Compare Match Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 12.12 shows an example of the setting procedure for waveform output by compare match.
Section 12 Timer Z 1. Examples of waveform output operation Figure 12.13 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF Time H'0000 FTIOB No change FTIOA No change No change No change Figure 12.
Section 12 Timer Z Figure 12.14 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value GRB GRA Time H'0000 Toggle output FTIOB FTIOA Toggle output Figure 12.14 Example of Toggle Output Operation Rev. 2.00 Sep.
Section 12 Timer Z 2. Output compare timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next TCNT input clock pulse is input. Figure 12.
Section 12 Timer Z 12.4.3 Input Capture Function The TCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 12.16 shows an example of the input capture operation setting procedure.
Section 12 Timer Z 1. Example of input capture operation Figure 12.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TCNT.
Section 12 Timer Z 2. Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR. Figure 12.18 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles. φ Input capture input Input capture signal TCNT GR N N Figure 12.18 Input Capture Signal Timing Rev. 2.00 Sep.
Section 12 Timer Z 12.4.4 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 12.19 shows an example of the synchronous operation setting procedure.
Section 12 Timer Z Figure 12.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1.
Section 12 Timer Z Table 12.3 Initial Output Level of FTIOB0 Pin TOB0 POLB Initial Output Level 0 0 1 0 1 0 1 0 0 1 1 1 PWM mode Select counter clock [1] Select counter clearing source [2] Set PWM mode [3] Set initial output level [4] Select output level [5] Set GR [6] Enable waveform output [7] Start counter operation [8] [1] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
Section 12 Timer Z Figure 12.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.22 Example of PWM Mode Operation (1) Rev. 2.00 Sep.
Section 12 Timer Z Figure 12.23 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.23 Example of PWM Mode Operation (2) Figures 12.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 12.
Section 12 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten Time H'0000 0% duty FTIOB TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB H'0000 Time FTIOB 100% duty When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 12 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten H'0000 Time FTIOB 0% duty TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB Time H'0000 100% duty FTIOB When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 12 Timer Z 12.4.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 12.4 and 12.5 show the PWM-output pins used and the register settings, respectively. Figure 12.
Section 12 Timer Z Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Initialize the output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bit STR0 in TSTR to 0 and stop the counter operation of TCNT_0. Set reset synchronous PWM mode after TCNT_0 stops. [2] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
Section 12 Timer Z Figures 12.27 and 12.28 show examples of operation in reset synchronous PWM mode. Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 12.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 2.00 Sep.
Section 12 Timer Z Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 12.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1.
Section 12 Timer Z 12.4.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement operation. Tables 12.6 and 12.7 show the output pins and register settings in complementary PWM mode, respectively. Figure 12.
Section 12 Timer Z Table 12.7 Register Settings in Complementary PWM Mode Register Description TCNT_0 Initial setting of non-overlapped periods (non-overlapped periods are differences with TCNT_1) TCNT_1 Initial setting of H'0000 GRA_0 Sets (upper limit value – 1) of TCNT_0 GRB_0 Set a changing point of the PWM waveform output from pins FTIOB0 and FTIOD0. GRA_1 Set a changing point of the PWM waveform output from pins FTIOA1 and FTIOC1.
Section 12 Timer Z [1] Complementary PWM mode Stop counter operation [1] [2] [3] Initialize output pin [2] Select counter clock [3] Set complementary PWM mode [4] Initialize output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [4] [5] [6] [7] Note: [8] [9] Clear bits STR0 and STR1 in TSTR to 0, and stop the counter operation of TCNT_0. Stop TCNT_0 and TCNT_1 and set complementary PWM mode. Write H'00 to TOCR.
Section 12 Timer Z 1. Canceling Procedure of Complementary PWM Mode: Figure 12.30 shows the complementary PWM mode canceling procedure. Complementary PWM mode Stop counter operation [1] Cancel complementary PWM mode [2] [1] Clear bit CMD1 in TFCR to 0, and set channels 0 and 1 to normal operation. [2] After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TSTR to 0 and stop TCNT0 and TCNT1. Figure 12.30 Canceling Procedure of Complementary PWM Mode 2.
Section 12 Timer Z TCNT_0 and GRA_0 are compared and their contents match TCNT values GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 12.31 Example of Complementary PWM Mode Operation (1) Rev. 2.00 Sep.
Section 12 Timer Z Figure 12.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). • TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to H'0000 or a value equal to or more than GRA_0. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, refer to section 12.4.8, Buffer Operation.
Section 12 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 12.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2) Rev. 2.00 Sep.
Section 12 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 12.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) Rev. 2.00 Sep.
Section 12 Timer Z In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 12.33 and 12.34.
Section 12 Timer Z the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000. If the φ/4 or φ/8 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is set to 1. 3. Setting GR Value in Complementary PWM Mode: To set the general register (GR) or modify GR during operation in complementary PWM mode, refer to the following notes. A. Initial value a. When other than TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value must be equal to H'FFFC or less.
Section 12 Timer Z • To change duty cycles while a 0%-duty cycle waveform is being output, write to GR while H'0000 ≤ TCNT_1 < previous GR value • To change duty cycles while a 100%-duty cycle waveform is being output, write to GR while previous GR value< TCNT_0 ≤ GRA_0 Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. b.
Section 12 Timer Z 12.4.8 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 12.8 shows the register combinations used in buffer operation. Table 12.8 Register Combinations in Buffer Operation General Register Buffer Register GRA GRC GRB GRD 1.
Section 12 Timer Z 3. Complementary PWM Mode When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general register. Here, the value of the buffer register is transferred to the general register in the following timing: A. When TCNT_0 and GRA_0 are compared and their contents match B. When TCNT_1 underflows 4. Reset Synchronous PWM Mode The value of the buffer register is transferred from compare match A0 to the general register.
Section 12 Timer Z 6. Examples of Buffer Operation Figure 12.38 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
Section 12 Timer Z φ n TCNT n+1 Compare match signal Buffer transfer signal GRC GRA N n N Figure 12.39 Example of Compare Match Timing for Buffer Operation Rev. 2.00 Sep.
Section 12 Timer Z Figure 12.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge. And both rising and falling edges have been selected as the FIOCA pin input capture input edge.
Section 12 Timer Z φ FTIO pin Input capture signal TCNT n n+1 N N+1 GRA M n n N GRC m M M n Figure 12.41 Input Capture Timing of Buffer Operation Rev. 2.00 Sep.
Section 12 Timer Z Figures 12.42 and 12.43 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows.
Section 12 Timer Z GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TCNT values TCNT_0 GRA_0 TCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 12.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) Rev. 2.00 Sep.
Section 12 Timer Z 12.4.9 Timer Z Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR and the external level. 1. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to 1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 12.44 shows the timing to enable or disable the output of timer Z by TOER.
Section 12 Timer Z 3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure 12.46 shows the timing. T1 T2 φ Address bus TOER address TFCR Timer Z output pin Inverted Figure 12.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR 4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 12.
Section 12 Timer Z 12.5 Interrupts There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 12.5.1 1. Status Flag Set Timing IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TCNT.
Section 12 Timer Z 2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 12.49 shows the timing. φ Input capture signal IMF TCNT N GR N ITMZ Figure 12.49 IMF Flag Set Timing at Input Capture 3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 12.50 shows the timing.
Section 12 Timer Z 12.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 12.51 shows the timing in this case. φ Address TSR address WTSR (internal write signal) IMF, OVF ITMZ Figure 12.51 Status Flag Clearing Timing 12.6 Usage Notes 1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not performed.
Section 12 Timer Z 2. Contention between TCNT Write and Increment Operations: If incrementation is done in T2 state of a TCNT write cycle, TCNT writing has priority. Figure 12.53 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock N TCNT M TCNT write data Figure 12.53 Contention between TCNT Write and Increment Operations 3.
Section 12 Timer Z 4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 12.55 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 12.55 Contention between TCNT Write and Overflow Rev. 2.00 Sep.
Section 12 Timer Z 5. Contention between GR Read and Input Capture: If an input capture signal is generated in the T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 12.56 shows the timing in this case. GR read cycle T1 T2 φ GR address Internal read signal Input capture signal GR Internal data bus X M X Figure 12.56 Contention between GR Read and Input Capture Rev. 2.00 Sep.
Section 12 Timer Z 6. Contention between Count Clearing and Increment Operations by Input Capture: If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TCNT contents before clearing counter are transferred to GR. Figure 12.57 shows the timing in this case. φ Input capture signal Counter clear signal TCNT input clock TCNT N GR H'0000 N Clearing has priority. Figure 12.
Section 12 Timer Z 7. Contention between GR Write and Input Capture: If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 12.58 shows the timing in this case. GR write cycle T1 T2 φ Address bus GR address WGR (internal write signal) Input capture signal TCNT GR N M GR write data Figure 12.58 Contention between GR Write and Input Capture 8.
Section 12 Timer Z 9. Note on Clearing TSR Flag: When a specific flag in TSR is cleared, a combination of the BCLR or MOV instructions is used to read 1 from the flag and then write 0 to the flag. However, if another bit is set during this processing, the bit may also be cleared simultaneously. To avoid this, the following processing that does not use the BCLR instruction must be executed. Note that this note is only applied to the F-ZTAT version.
Section 12 Timer Z TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0. When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0 does not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
Section 12 Timer Z Rev. 2.00 Sep.
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 13 Watchdog Timer Bit Initial Bit Name Value R/W Description 2 WDON R/W Watchdog Timer On 1 The TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The WDT is set enabled by default. To disable the WDT, clear this bit to 0. [Clearing conditions] • When writing 0 to the B2WI bit and 0 to the WDON bit while the TCSRWE bit =1.
Section 13 Watchdog Timer 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Initial Bit Name Value R/W Description 7 to 4 All 1 Reserved 3 CKS3 1 R/W Clock Select 3 to 0 2 CKS2 1 R/W Select the clock to be input to TCWD. 1 CKS1 1 R/W 1000: Internal clock: counts on φ/64 0 CKS0 1 R/W 1001: Internal clock: counts on φ/128 These bits are always read as 1.
Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles. As TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value.
Section 13 Watchdog Timer Rev. 2.00 Sep.
Section 14 14-Bit PWM Section 14 14-Bit PWM The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. Figure 14.1 shows a block diagram of the 14-bit PWM. 14.1 Features • Choice of two conversion periods A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion period of 16384/φ with a minimum modulation width of 1/φ, can be selected.
Section 14 14-Bit PWM 14.2 Input/Output Pin Table 14.1 shows the 14-bit PWM pin configuration. Table 14.1 Pin Configuration Name Abbreviation I/O Function 14-bit PWM square-wave output PWM Output 14-bit PWM square-wave output pin 14.3 Register Descriptions The 14-bit PWM has the following registers. • PWM control register (PWCR) • PWM data register U (PWDRU) • PWM data register L (PWDRL) 14.3.1 PWM Control Register (PWCR) PWCR selects the conversion period.
Section 14 14-Bit PWM 14.3.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed.
Section 14 14-Bit PWM Conversion period t f1 t H1 t f2 t H2 t f63 t H3 t H63 t f64 t H64 T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64 Figure 14.2 Waveform Output by 14-Bit PWM Rev. 2.00 Sep.
Section 15 Serial Communication Interface 3 (SCI3) Section 15 Serial Communication Interface 3 (SCI3) This LSI includes a serial communication interface 3 (SCI3) , which has independent two channels. The SCI3can handle both asynchronous and clocked synchronous serial communication.
Section 15 Serial Communication Interface 3 (SCI3) Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors Table 15.
Section 15 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRR BRC Clock Transmit/receive control circuit Internal data bus SMR SCR3 SSR TXD TSR TDR RXD RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3: Serial control register 3 SSR: Serial status register BRR: Bit rate register
Section 15 Serial Communication Interface 3 (SCI3) 15.3 Register Descriptions The SCI3 has the following registers. • • • • • • • • Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR) 15.3.
Section 15 Serial Communication Interface 3 (SCI3) 15.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission.
Section 15 Serial Communication Interface 3 (SCI3) Bit Initial Bit Name Value R/W Description 3 STOP R/W Stop Bit Length (enabled only in asynchronous mode) 0 Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
Section 15 Serial Communication Interface 3 (SCI3) 15.3.6 Serial Control Register 3 (SCR3) SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, see section 15.7, Interrupts. Bit Initial Bit Name Value R/W Description 7 TIE R/W Transmit Interrupt Enable 0 When this bit is set to 1, the TXI interrupt request is enabled.
Section 15 Serial Communication Interface 3 (SCI3) Bit Initial Bit Name Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source. • Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin.
Section 15 Serial Communication Interface 3 (SCI3) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Initial Bit Name Value R/W Description 7 TDRE R/W Transmit Data Register Empty 1 Indicates whether TDR contains transmit data.
Section 15 Serial Communication Interface 3 (SCI3) Bit Initial Bit Name Value R/W Description 3 PER R/W Parity Error 0 [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1-frame serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TDRE a
Section 15 Serial Communication Interface 3 (SCI3) 15.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 15.3 shows the relationship between the N setting in BRR and the n setting in the CKS1 and CKS0 bits of SMR in asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 15.3 and 15.4 are values in active (highspeed) mode. Table 15.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 12.888 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 8 250000 0 0 2.097152 65536 0 0 9.8304 307200 0 0 2.4576 76800 0 0 10 312500 0 0 3 93750 0 0 12 375000 0 0 3.6864 115200 0 0 12.288 384000 0 0 4 125000 0 0 14 437500 0 0 4.9152 153600 0 0 14.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency φ (MHz) 2 4 8 10 Bit Rate (bit/s) n N n N n N n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — 16 n N — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N n N 110 — — — — 250 — — — — 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1M 0 4 0 4 2M — — — — 2.
Section 15 Serial Communication Interface 3 (SCI3) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Section 15 Serial Communication Interface 3 (SCI3) 15.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 15 Serial Communication Interface 3 (SCI3) 15.4.3 Data Transmission Figure 15.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data to TDR [2] Yes All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 15 Serial Communication Interface 3 (SCI3) 15.4.4 Serial Data Reception Figure 15.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 15 Serial Communication Interface 3 (SCI3) Table 15.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.8 shows a sample flow chart for serial data reception. Table 15.
Section 15 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 15 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 15.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(2) Rev. 2.00 Sep.
Section 15 Serial Communication Interface 3 (SCI3) 15.5 Operation in Clocked Synchronous Mode Figure 15.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
Section 15 Serial Communication Interface 3 (SCI3) 15.5.3 Serial Data Transmission Figure 15.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 15 Serial Communication Interface 3 (SCI3) 15.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. The SCI3 stores the receive data in RSR. 3.
Section 15 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.13 shows a sample flow chart for serial data reception. Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1? No [4] Overrun error processing (Continued below) Read RDRF flag in SSR [3] [2] [4] No RDRF = 1? Yes Read the OER flag in SSR to determine if there is an error.
Section 15 Serial Communication Interface 3 (SCI3) 15.5.5 Simultaneous Serial Data Transmission and Reception Figure 15.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 15 Serial Communication Interface 3 (SCI3) 15.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 15 Serial Communication Interface 3 (SCI3) 15.6.1 Multiprocessor Serial Data Transmission Figure 15.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Section 15 Serial Communication Interface 3 (SCI3) 15.6.2 Multiprocessor Serial Data Reception Figure 15.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 15.
Section 15 Serial Communication Interface 3 (SCI3) [5] Start receive error processing No OER = 1? Yes Overrun error processing No FER = 1? Yes Yes Break? No [A] Framing error processing Clear OER and FER flags in SSR to 0 Figure 15.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00 Sep.
Section 15 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation User processing RXI interrupt request is not generated, and RDR retains its state RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again (a)
Section 15 Serial Communication Interface 3 (SCI3) 15.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 15.7 shows the interrupt sources. Table 15.
Section 15 Serial Communication Interface 3 (SCI3) 15.8 Usage Notes 15.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.8.
Section 15 Serial Communication Interface 3 (SCI3) 15.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 15.19.
Section 15 Serial Communication Interface 3 (SCI3) Rev. 2.00 Sep.
2 Section 16 I C Bus Interface 2 (IIC2) Section 16 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 16.1 shows a block diagram of the I2C bus interface 2. Figure 16.2 shows an example of I/O pin connections to external circuits. 16.
2 Section 16 I C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interr
2 Section 16 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SDA in (Master) SCL SDA SDA out SCL in SCL out SCL SDA SCL out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I2C bus interface 2. Table 16.
2 Section 16 I C Bus Interface 2 (IIC2) 16.3 Register Descriptions The I2C bus interface 2 has the following registers. • • • • • • • • • I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) 16.3.
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
2 Section 16 I C Bus Interface 2 (IIC2) Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock 0 0 1 0 1 φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz 0 φ/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 0 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 φ/100 50.0 kHz 80.
2 Section 16 I C Bus Interface 2 (IIC2) 16.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Initial Bit Name Value R/W Description 7 BBSY R/W Bus Busy 0 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning.
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value R/W Description 4 SDAOP R/W SDAO Write Protect 1 This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
2 Section 16 I C Bus Interface 2 (IIC2) 16.3.3 I2C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Initial Bit Name Value R/W Description 7 MLS R/W MSB-First/LSB-First Select 0 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used.
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value 2 BC2 1 0 R/W Description 0 R/W Bit Counter 2 to 0 BC1 0 R/W BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Setting the BC2 to BC0 bits should be made during an interval between transfer frames.
2 Section 16 I C Bus Interface 2 (IIC2) 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Initial Bit Name Value R/W Description 7 TIE R/W Transmit Interrupt Enable 0 When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value R/W Description 4 NAKIE R/W NACK Receive Interrupt Enable 0 This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled.
2 Section 16 I C Bus Interface 2 (IIC2) 16.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value R/W Description 4 NACKF R/W No Acknowledge Detection Flag 0 [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1 Stop Condition Detection Flag [Setting Conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a st
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value R/W Description 2 AL/OVE R/W Arbitration Lost Flag/Overrun Error Flag 0 This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format.
2 Section 16 I C Bus Interface 2 (IIC2) Bit Initial Bit Name Value R/W Description 0 ADZ R/W General Call Address Recognition Flag 0 2 This bit is valid in I C bus format slave receive mode. [Setting condition] • When the general call address is detected in slave receive mode [Clearing condition] • 16.3.6 When 0 is written in ADZ after reading ADZ=1 Slave Address Register (SAR) SAR selects the communication format and sets the slave address.
2 Section 16 I C Bus Interface 2 (IIC2) 16.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
2 Section 16 I C Bus Interface 2 (IIC2) 16.4 Operation The I2C bus interface 2 can communicate either in I2C bus mode or clocked synchronous serial mode by setting the FS bit in SAR. 16.4.1 I2C Bus Format Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
2 Section 16 I C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 16.4.
2 Section 16 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 16.
2 Section 16 I C Bus Interface 2 (IIC2) 16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, see figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
2 Section 16 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) SDA (Slave output) 9 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing [2] Read ICDRR (dummy read) TEND and TRS Figure 16.7 Master Receive Mode Operation Timing (1) Rev. 2.00 Sep.
2 Section 16 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS ICDRR User processing Data n Data n-1 Data n Data n-1 [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 16.8 Master Receive Mode Operation Timing (2) 16.4.
2 Section 16 I C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 7 Bit 0 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 16.
2 Section 16 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) [5] Clear TDRE after clearing TRS Figure 16.10 Slave Transmit Mode Operation Timing (2) Rev. 2.00 Sep.
2 Section 16 I C Bus Interface 2 (IIC2) 16.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, see figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1.
2 Section 16 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 16.12 Slave Receive Mode Operation Timing (2) 16.4.
2 Section 16 I C Bus Interface 2 (IIC2) (2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, see figure 16.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
2 Section 16 I C Bus Interface 2 (IIC2) (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, see figure 16.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
2 Section 16 I C Bus Interface 2 (IIC2) 16.4.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.16 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
2 Section 16 I C Bus Interface 2 (IIC2) Start Initialize [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start candition. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP. [3] [5] Wait for 1 byte to be transmitted. Write transmit data in ICDRT [4] [6] Test the acknowledge transferred from the specified slave device.
2 Section 16 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. [9] Wait for the last byte to be receive.
2 Section 16 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR No [5] Wait for the last byte to be transmitted. [3] TDRE=1 ? Yes No [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? Yes [2] Set transmit data for ICDRT (except for the last data). [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
2 Section 16 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received.
2 Section 16 I C Bus Interface 2 (IIC2) 16.5 Interrupt Requests There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 16.3 shows the contents of each interrupt request. Table 16.
2 Section 16 I C Bus Interface 2 (IIC2) 16.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 16.21 shows the timing of the bit synchronous circuit and table 16.
2 Section 16 I C Bus Interface 2 (IIC2) 16.7 Usage Notes 16.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1.
2 Section 16 I C Bus Interface 2 (IIC2) Rev. 2.00 Sep.
Section 17 A/D Converter Section 17 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 17.1. 17.1 • • • • • • • • Features 10-bit resolution Eight input channels Conversion time: at least 3.
Section 17 A/D Converter Module data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 17.
Section 17 A/D Converter 17.2 Input/Output Pins Table 17.1 summarizes the input pins used by the A/D converter. The eight analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 17.
Section 17 A/D Converter 17.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 17.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 17 A/D Converter 17.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 17 A/D Converter Bit Initial Bit Name Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 17.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal.
Section 17 A/D Converter 17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 17.4.
Section 17 A/D Converter 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 17.2 shows the A/D conversion timing. Table 17.3 shows the A/D conversion time. As indicated in figure 17.2, the A/D conversion time includes tD and the input sampling time.
Section 17 A/D Converter Table 17.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. A/D conversion start delay time tD Input sampling time tSPL A/D conversion time tCONV CKS = 1 Typ. Max. Min. Typ. Max. 6 — 9 — 31 — 4 — 5 — 15 — 131 — 134 69 — 70 Note: All values represent the number of states. 17.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 17 A/D Converter 17.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 17.5).
Section 17 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Analog input voltage Figure 17.4 A/D Conversion Accuracy Definitions (1) Rev. 2.00 Sep.
Section 17 A/D Converter Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 17.5 A/D Conversion Accuracy Definitions (2) Rev. 2.00 Sep.
Section 17 A/D Converter 17.6 Usage Notes 17.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 17 A/D Converter Rev. 2.00 Sep.
Section 18 Power-On Reset and Low-Voltage Detection Circuits Section 18 Power-On Reset and Low-Voltage Detection Circuits This LSI incorporates a power-on reset circuit and low-voltage detection circuit. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Section 18 Power-On Reset and Low-Voltage Detection Circuits φ CK R OVF PSS R RES Internal reset signal Q Noise canceler S Power-on reset circuit Noise canceler Vcc Ladder resistor Internal data bus LVDCR Vreset + − Vint LVDRES + − LVDINT Reference voltage generator Interrupt control circuit LVDSR Interrupt request Low-voltage detection circuit [Legend] PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection control register Low-voltage-detection status reg
Section 18 Power-On Reset and Low-Voltage Detection Circuits 18.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) 18.2.
Section 18 Power-On Reset and Low-Voltage Detection Circuits Bit Initial Bit Name Value R/W Description 1 LVDDE R/W Voltage-Fall-Interrupt Enable 0 0: Interrupt on the power-supply voltage falling below the selected detection level disabled 1: Interrupt on the power-supply voltage falling below the selected detection level enabled 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on the power-sup
Section 18 Power-On Reset and Low-Voltage Detection Circuits 18.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values. Bit Initial Bit Name Value R/W Description 7 to 2 Reserved All 1 These bits are always read as 1 and cannot be modified. 1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag [Setting condition] When the power-supply voltage falls below Vint (D) (typ. = 3.
Section 18 Power-On Reset and Low-Voltage Detection Circuits 18.3 Operation 18.3.1 Power-On Reset Circuit Figure 18.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states.
Section 18 Power-On Reset and Low-Voltage Detection Circuits 18.3.2 (1) Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit Figure 18.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 50 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (2) LVDI (Interrupt by Low Voltage Detect) Circuit Figure 18.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (3) Procedures for Settings/Releasing Operation when Using LVDR and LVDI To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 18.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2.
Section 18 Power-On Reset and Low-Voltage Detection Circuits Rev. 2.00 Sep.
Section 19 Power Supply Circuit Section 19 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external Vcc pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 19 Power Supply Circuit 19.2 When not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and Vcc pin, as shown in figure 19.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 20 List of Registers Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • The symbol in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses.
Section 20 List of Registers 20.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed. Register Abbreviation Bit No.
Section 20 List of Registers Register Abbreviation Bit No.
Section 20 List of Registers Register Abbreviation Bit No.
Section 20 List of Registers Register Abbreviation Bit No.
Section 20 List of Registers Register Abbreviation Bit No.
Section 20 List of Registers Register Abbreviation Bit No.
Section 20 List of Registers 20.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Section 20 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name GRB_1 GRB1H7 GRB1H6 GRB1H5 GRB1H4 GRB1H3 GRB1H2 GRB1H1 GRB1H0 Timer Z GRB1L7 GRB1L6 GRB1L5 GRB1L4 GRB1L3 GRB1L2 GRB1L1 GRB1L0 GRC1H7 GRC1H6 GRC1H5 GRC1H4 GRC1H3 GRC1H2 GRC1H1 GRC1H0 GRC1L7 GRC1L6 GRC1L5 GRC1L4 GRC1L3 GRC1L2 GRC1L1 GRC1L0 GRD1H7 GRD1H6 GRD1H5 GRD1H4 GRD1H3 GRD1H2 GRD1H1 GRD1H0 GRD1L7 GRD1L6 GRD1L5 GRD1L4 GRD1L3 GRD1L2 GRD1L1 GRD1L0
Section 20 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name FLMCR1 SWE ESU PSU EV PV E P ROM FLMCR2 FLER EBR1 EB4 EB3 EB2 EB1 EB0 FENR FLSHE TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCSRV CMFB CMFA OVF OS3 OS2 OS1 OS0 TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCOR
Section 20 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TCSRWD B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST WDT* TCWD TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0 TMWD CKS3 CKS2 CKS1 CKS0 ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break ABRKSR ABIF ABIE BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BA
Section 20 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name IEGR1 NMIEG IEG3 IEG2 IEG1 IEG0 Interrupt IEGR2 WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0 IENR1 IENDT IENWP IEN3 IEN2 IEN1 IEN0 IENR2 IENTB1 IRR1 IRRDT IRRI3 IRRI2 IRRI1 IRRI0 IRR2 IRRTB1 IWPR IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 MSTCR1 MSTIIC MSTS3 MSTAD MSTWD MSTTV MSTCR2
Section 20 List of Registers 20.
Section 20 List of Registers Register Name Reset Active Sleep Subsleep Standby Module LVDCR Initialized LVDC LVDSR Initialized SMR_2 Initialized Initialized Initialized BRR_2 Initialized Initialized Initialized SCR3_2 Initialized Initialized Initialized TDR_2 Initialized Initialized Initialized SSR_2 Initialized Initialized Initialized RDR_2 Initialized Initialized Initialized ICCR1 Initialized ICC
Section 20 List of Registers Register Name Reset Active Sleep Subsleep Standby Module SMR Initialized Initialized Initialized SCI3 BRR Initialized Initialized Initialized SCR3 Initialized Initialized Initialized TDR Initialized Initialized Initialized SSR Initialized Initialized Initialized RDR Initialized Initialized Initialized ADDRA Initialized Initialized Initialized ADDRB Initialized Initialized Initialized ADDRC
Section 20 List of Registers Register Name Reset Active Sleep Subsleep Standby Module PDR7 Initialized I/O port PDR8 Initialized PDRB Initialized PMR1 Initialized PMR5 Initialized PMR3 Initialized PCR1 Initialized PCR2 Initialized PCR3 Initialized PCR5 Initialized PCR6 Initialized PCR7 Initialized PCR8 Initialized SYSCR
Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage Vcc –0.3 to +7.0 V * Analog power supply voltage AVcc –0.3 to +7.0 V Input voltage VIN –0.3 to Vcc +0.3 V Ports other than port B Port B –0.3 to AVcc +0.3 V X1 –0.3 to 4.
Section 21 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range when Low-Voltage Detection Circuit is not Used: φ (MHz) φ (kHz) 20.0 2500 10.0 1250 1.0 78.125 3.0 4.0 5.5 VCC (V) 3.0 • AVCC = 3.0 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0 ) (3) 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.
Section 21 Electrical Characteristics (4) Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used: φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev. 2.00 Sep.
Section 21 Electrical Characteristics 21.2.2 DC Characteristics Table 21.2 DC Characteristics (1) Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Input high VIH voltage Max. Unit RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1,SCK3, SCK3_2, TRGV Vcc = 4.0 to 5.5 V Vcc × 0.8 — Vcc + 0.3 V Vcc × 0.9 — Vcc + 0.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Input low voltage VIL Output high voltage VOH Typ. Max. Unit RES, NMI, Vcc = 4.0 to 5.5 V –0.3 WKP0 to WKP5, IRQ0 to IRQ3, –0.3 ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, SCK3_2, TRGV — Vcc × 0.2 V — Vcc × 0.1 V RXD, RXD_2, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87 Vcc = 4.0 to 5.5 V –0.3 — Vcc × 0.3 V –0.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Output low voltage VOL P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P70 to P72, P74 to P76, P85 to P87 Vcc = 4.0 to 5.5 V IOL = 1.6 mA — — 0.6 V IOL = 0.4 mA — — 0.4 V P60 to P67 Vcc = 4.0 to 5.5 V IOL = 20.0 mA — — 1.5 V Vcc = 4.0 to 5.5 V IOL = 10.0 mA — — 1.0 V Vcc = 4.0 to 5.5 V IOL = 1.6 mA — — 0.4 V IOL = 0.4 mA — — 0.4 V Vcc = 4.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Pull-up MOS current –Ip P10 to P12, P14 to P17, P50 to P55 Vcc = 5.0 V, VIN = 0.0 V 50.0 — 300.0 µA Vcc = 3.0 V, VIN = 0.0 V — 60.0 — µA Input capacitance CIN All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF Active IOPE1 mode current consumption Vcc Active mode 1 Vcc = 5.0 V, fOSC = 20 MHz — 21.0 30.
Section 21 Electrical Characteristics Note: * Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). Mode RES Pin Internal State Other Pins Oscillator Pins Active mode 1 Vcc Operates Vcc Active mode 2 Sleep mode 1 Operates (φOSC/64) Vcc Sleep mode 2 Standby mode Only timers operate Vcc Only timers operate (φOSC/64) Vcc CPU and timers both stop Rev. 2.00 Sep.
Section 21 Electrical Characteristics Table 21.2 DC Characteristics (2) Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Allowable output low current (per pin) IOL Allowable output low current (total) ∑IOL Applicable Pins Values Test Condition Min. Typ. Max. Unit Vcc = 4.0 to 5.5 V — — 2.0 mA Port 6 — — 20.0 mA Output pins except port 6, SCL, and SDA — — 0.5 mA Port 6 — — 10.0 mA SCL, SDA — — 6.0 mA — — 40.
Section 21 Electrical Characteristics 21.2.3 AC Characteristics Table 21.3 AC Characteristics Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol System clock oscillation frequency fOSC System clock (φ) cycle time tcyc Applicable Pins OSC1, OSC2 Values Test Condition Min. Typ. Max. Unit Reference Figure Vcc = 4.0 to 5.5 V 2.0 — 20.0 MHz * 2.0 — 10.0 MHz 1 — 64 tOSC — — 12.
Section 21 Electrical Characteristics Item Symbol Applicable Pins RES pin low width tREL RES Values Typ. Max. Unit Reference Figure At power-on and in trc modes other than those below — — ms Figure 21.2 In active mode and 200 sleep mode operation — — ns Test Condition Min.
Section 21 Electrical Characteristics Table 21.4 I2C Bus Interface Timing Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Max. Unit Reference Figure 12tcyc + 600 — — ns Figure 21.
Section 21 Electrical Characteristics Table 21.5 Serial Communication Interface (SCI) Timing Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Section 21 Electrical Characteristics 21.2.4 A/D Converter Characteristics Table 21.6 A/D Converter Characteristics Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Test Pins Condition Min. Typ. Max. Unit Notes Analog power supply AVcc voltage AVcc 3.0 Vcc 5.5 V * Analog input voltage AVIN AN0 to AN7 Vss – 0.3 — AVcc + 0.3 V Analog power supply AIOPE current AVcc — — 2.0 mA Item Symbol AVCC = 5.
Section 21 Electrical Characteristics Applicable Pins Test Condition Values Min. Typ. Max. Unit 134 — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Item Symbol Conversion time (single mode) AVcc = 4.0 to 5.5 V Notes Notes: 1. Set AVcc = Vcc when the A/D converter is not used. 2.
Section 21 Electrical Characteristics 21.2.6 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics Vcc = 3.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Test Condition Values Min. Typ. Max.
Section 21 Electrical Characteristics Item Erasing Symbol Test Condition Values Min. Typ. Max.
Section 21 Electrical Characteristics 21.2.7 Power-Supply-Voltage Detection Circuit Characteristics Table 21.9 Power-Supply-Voltage Detection Circuit Characteristics Vss = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Min. Typ. Max. Unit Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.7 — V Power-supply rising detection voltage Vint (U) LVDSEL = 0 — 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 — 2.3 2.
Section 21 Electrical Characteristics 21.3 Operation Timing t OSC VIH OSC1 VIL t CPH t CPL t CPr t CPf Figure 21.1 System Clock Input Timing VCC VCC × 0.7 OSC1 tREL RES VIL VIL tREL Figure 21.2 RES Low Width Timing NMI, TMIB1 IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, TMCIV, TMRIV TRGV VIH VIL t IL t IH Figure 21.3 Input Timing Rev. 2.00 Sep.
Section 21 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSCL P* tSDAS tSr tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 21.4 I2C Bus Interface Input/Output Timing t SCKW SCK3 t Scyc Figure 21.5 SCK3 Input Clock Timing Rev. 2.00 Sep.
Section 21 Electrical Characteristics t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD TXD (transmit data) VOH* VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: V OH= 2.0 V Output low: V OL= 0.8 V Load conditions are shown in figure 21.7. Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode 21.4 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 21.7 Output Load Circuit Rev. 2.00 Sep.
Section 21 Electrical Characteristics Rev. 2.00 Sep.
Appendix Appendix A. Instruction Set A.
Symbol Description ⊕ Logical exclusive OR of the operands on both sides ¬ NOT (logical complement) ( ), < > Contents of operand ↔ Appendix Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Rev. 2.00 Sep.
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions — — B MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix @(d:16, ERs) → ERd32 — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — ↔ — — ↔ @ERs → ERd32 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — — ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERs32 → ERd32 ↔ ↔ ↔ ↔ ↔ ↔ — — ↔ ↔ ↔ ↔ ↔ ↔ #xx:32 → Rd32 0 — 0 — 0 — POP POP.
Appendix 2. Arithmetic Instructions H N Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ ↔ ↔ ↔ ↔ (3) ↔ ↔ I — (1) Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix 2 ERd32–2 → ERd32 — — ↔ ↔ 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXS DIVXS. B Rs, Rd DIVXS. W Rs, ERd CMP CMP.
Appendix ↔ ↔ ↔ ↔ ↔ ↔ ↔ 0 → ( of ERd32) — — 0 2 ( of Rd16) → ( of Rd16) — — 2 ( of ERd32) → ( of ERd32) — — — NEG.W Rd W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU EXTU.W Rd W 2 0 → ( of Rd16) EXTU.L ERd L 2 EXTS EXTS.W Rd W EXTS.L ERd L Normal ↔ ↔ ↔ — — 0 0–Rd8 → Rd8 ↔ ↔ ↔ C 2 2 0 — 2 ↔ V B 0 — 2 ↔ Z ↔ H NEG NEG.
Appendix 3. Logic Instructions W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix 5.
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix 6.
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — I H N Z V C Normal Condition Code Operation Advanced No.
Appendix 7. System Control Instructions Normal Advanced No.
Appendix 8. Block Transfer Instructions EEPMOV I H N Z V C EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV. W — 4 if R4 ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4–1 → R4 until R4=0 else next — — — — — — 8+ 4n*2 Advanced Condition Code Operation Normal No.
REJ09B0068-0200 Rev. 2.00 Sep. 23, 2005 Page 396 of 444 MULXU 5 STC LDC 3 BVC 8 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST MOV BVS 9 A B JMP BPL BMI MOV Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 EEPMOV (2) (2) SUB ADD Table A.2 TRAPA (2) BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A.2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.
MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 ADD ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table
REJ09B0068-0200 Rev. 2.00 Sep. 23, 2005 Page 398 of 444 DIVXS 3 BSET 7Faa7 *2 BNOT BNOT BCLR BCLR Notes:1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. For details, see section 20.1, Register Addresses (Address Order). Rev. 2.00 Sep.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.L ERs, ERd 2 ANDC #xx:8, CCR 1 AND ANDC BAND Bcc Stack Branch Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K INC INC.B Rd 1 INC.W #1/2, Rd 1 INC.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP 1 MULXU NEG NOP NOT OR NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K Stack ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Byte Data Word Data Internal Access L Access M Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAR SHLL SHLR SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K SUBX SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 TRAPA TRAPA #xx:2 2 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 XORC 1 Stack 2 Byte Data Word Data Internal Access L Access M Operation N 4 Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Arithmetic operations MOVTPE ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG — @aa:24 @@aa:8 BWL BWL WL BWL B B — L — BWL — B — BW BWL BWL — — — — @(d:16.PC) B — — @(d:8.PC) BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @aa:16 @aa:8 @ERn+/@ERn @(d:24.ERn) @(d:16.
Appendix B. I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low at a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 2.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P16, P14) Rev. 2.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TMIB1 [Legend] PUCR : Port pull-up control register PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.3 Port 1 Block Diagram (P15) Rev. 2.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR : Port pull-up control register PDR : Port data register PCR : Port control register Figure B.4 Port 1 Block Diagram (P12, P10) Rev. 2.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR 14-bit PWM PWM [Legend] PUCR : Port pull-up control register PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.5 Port 1 Block Diagram (P11) Rev. 2.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.6 Port 2 Block Diagram (P24, P23) Rev. 2.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TXD [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.7 Port 2 Block Diagram (P22) Rev. 2.00 Sep.
Appendix SBY Internal data bus PDR PCR SCI3 RE RXD [Legend] PDR: Port data register PCR: Port control register Figure B.8 Port 2 Block Diagram (P21) Rev. 2.00 Sep.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.9 Port 2 Block Diagram (P20) Rev. 2.00 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR : Port data register PCR : Port control register Figure B.10 Port 3 Block Diagram (P37 to P30) Rev. 2.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.11 Port 5 Block Diagram (P57, P56) Rev. 2.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.12 Port5 Block Diagram (P55) Rev. 2.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.13 Port 5 Block Diagram (P54 to P50) Rev. 2.00 Sep.
Appendix Internal data bus SBY Timer Z Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR : Port data register PCR : Port control register Figure B.14 Port 6 Block Diagram (P67 to P60) Rev. 2.00 Sep.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 7 Block Diagram (P76) Rev. 2.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 7 Block Diagram (P75) Rev. 2.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.17 Port 7 Block Diagram (P74) Rev. 2.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3_2 TXD [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.18 Port 7 Block Diagram (P72) Rev. 2.00 Sep.
Appendix SBY Internal data bus PDR PCR SCI3_2 RE RXD [Legend] PDR : Port data register PCR : Port control register Figure B.19 Port 7 Block Diagram (P71) Rev. 2.00 Sep.
Appendix SBY SCI3_2 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR : Port data register PCR : Port control register Figure B.20 Port 7 Block Diagram (P70) Rev. 2.00 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.21 Port 8 Block Diagram (P87 to P85) Rev. 2.00 Sep.
Appendix Internal data bus A/D converter DEC CH3 to CH0 VIN Figure B.22 Port B Block Diagram (PB7 to PB0) Rev. 2.00 Sep.
Appendix B.
Appendix C. Product Code Lineup Product Classification Product Code Model Marking Package Code H8/36064GF Flash memory Product with version POR & LVDC HD64F36064GH DF36064GH QFP-64 (FP-64A) HD64F36064GPF DF36064GPF LQFP-64 (FP-64E) D. Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Rev. 2.00 Sep.
64 e 1 ZD D y *3 bp 16 33 x F M 17 32 MASS[Typ.] 1.2g Detail F L1 L Terminal cross section b1 bp θ 17.2 16.9 16.9 HD HE 0.5 1.6 0.8 L L1 1.0 ZE 1.1 0.10 1.0 ZD 0.15 8° y 0.8 0.22 x e θ 0° 0.17 0.15 c c1 0.35 b1 0.12 0.29 bp 0.45 0.25 0.00 A1 0.37 3.05 17.5 17.5 Max A 0.10 17.2 14 2.70 A2 14 Nom Dimension in Millimeters Min E D Reference Symbol NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
64 49 Figure D.1 FP-64E Package Dimensions e ZD 1 48 *1 y *3 bp Index mark D 16 33 x F M 17 32 E *2 HD Previous Code FP-64E/FP-64EV MASS[Typ.] 0.4g Detail F L1 L Terminal cross section b1 bp θ 12.0 12.2 0.5 L 1.0 1.25 ZE L1 1.25 ZD 0.7 0.08 8° 0.10 0.5 0.22 y 0.3 0° 0.15 0.27 x e θ c1 0.20 0.17 c 0.22 b1 0.12 0.17 0.20 bp 1.70 12.2 A1 0.10 12.0 Max A 0.00 11.8 11.8 A2 HE 10 1.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface vii When using the on-chip emulator (E7, E8) for H8/36064 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
Item Page Revision (See Manual for Details) 12.4.9 Timer Z Output Timing 216 Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER T2 T1 φ Address bus TOER address Timer Z output pin Timer output I/O port I/O port Timer Z output Figure 12.45 Example of 216 Output Disable Timing of Timer Z by External Trigger φ TOER Timer Z output pin N H'FF Timer Z output I/O port Timer Z output 13.2.
Item Page Revision (See Manual for Details) 2 Section 16 I C Bus Interface 2 (IIC2) 292 16.3.
Rev. 2.00 Sep.
Index Numerics D 14-bit PWM ............................................ 235 Data transfer instructions .......................... 19 A E A/D converter ......................................... 289 Absolute address....................................... 30 Acknowledge .......................................... 297 Address break ........................................... 59 Addressing modes..................................... 29 Arithmetic operations instructions............ 20 Asynchronous mode ....
Input capture function............................. 183 Instruction set ........................................... 18 Internal interrupts ..................................... 55 Internal power supply step-down circuit 341 Interrupt mask bit ..................................... 14 Interrupt response time ............................. 56 Interval timer operation .......................... 131 IRQ3 to IRQ0 interrupts ........................... 53 L Large current ports......................................
ADDRA ...................... 292, 347, 352, 357 ADDRB ...................... 292, 347, 352, 357 ADDRC ...................... 292, 347, 352, 357 ADDRD ...................... 292, 347, 352, 357 BARH ........................... 62, 347, 353, 357 BARL ........................... 62, 347, 353, 357 BDRH ........................... 63, 347, 353, 357 BDRL ........................... 63, 348, 353, 357 BRR ............................ 249, 346, 352, 357 EBR1 ............................ 83, 346, 352, 356 FENR........
TDR .............................243, 346, 352, 357 TFCR ...........................159, 345, 351, 355 TIER ............................172, 344, 350, 355 TIORA.........................167, 344, 350, 355 TIORC .........................169, 344, 350, 355 TLB1 .................................................. 131 TMB1 ..........................130, 346, 351, 356 TMDR .........................157, 345, 351, 355 TMWD ........................232, 347, 353, 357 TOCR ..........................
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36064 Group Publication Date: Rev.1.00, Apr. 22, 2004 Rev.2.00, Sep. 23, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.
H8/36064 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0068-0200
