Datasheet

Section 5 Clock Pulse Generators
Rev. 2.00 Sep. 23, 2005 Page 68 of 444
REJ09B0068-0200
5.2 Prescalers
5.2.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode and subsleep mode, the system clock pulse generator stops.
Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be
set separately for each on-chip peripheral function. In active mode and sleep mode, the clock input
to prescaler S is determined by the division factor designated by the MA2 to MA0 bits in
SYSCR2.
5.3 Usage Notes
5.3.1 Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator element
manufacturer. Design the circuit so that the resonator element never receives voltages exceeding
its maximum rating.
5.3.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC
1
and OSC
2
pins. Other signal lines should be routed away from the
oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.7).
OSC
1
OSC
2
C
1
C
2
Signal A Signal B
Avoid
Figure 5.7 Example of Incorrect Board Design