Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Sep. 23, 2005 Page 70 of 444
REJ09B0068-0200
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit Bit Name
Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
This bit selects the transition mode after the execution
of the SLEEP instruction.
0: A transition is made to sleep mode
1: A transition is made to standby mode
For details, see table 6.2.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting
from standby mode, to active mode or sleep mode due
to an interrupt. The designation should be made
according to the clock frequency so that the waiting
time is at least 6.5 ms. The relationship between the
specified value and the number of wait states is shown
in table 6.1. When an external clock is to be used, the
minimum value (STS2 = STS1 = STS0 =1) is
recommended.
3 to 0  All 0  Reserved
These bits are always read as 0.