Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Sep. 23, 2005 Page 76 of 444
REJ09B0068-0200
Note: * When a state transition is made while the SMSEL bit is 1, the timer V, SCI3, SCI3_2,
and A/D converter are reset, and all registers are set to their initial values. To use these
functions after entering active mode, reset the registers.
Table 6.3 Internal State in Each Operating Mode
Function Active Mode Sleep Mode Subsleep Mode Standby Mode
System clock oscillator Functioning Functioning Halted Halted
Instructions Functioning Halted Halted Halted CPU
operations
Registers Functioning Retained Retained Retained
RAM Functioning Retained Retained Retained
IO ports Functioning Retained Retained Register contents
are retained, but
output is the high-
impedance state.
IRQ3 to IRQ0 Functioning Functioning Functioning Functioning External
interrupts
WKP5 to
WKP0
Functioning Functioning Functioning Functioning
Timer V Functioning Functioning Reset Reset
Watchdog
timer
Functioning Functioning Retained Retained
(Functioning when
internal oscillator
is selected as
count clock)
Peripheral
functions
SCI3, SCI3_2 Functioning Functioning Reset Reset
IIC2 Functioning Functioning Retained Retained
Timer B1 Functioning Functioning Retained Retained
Timer Z Functioning Functioning Retained Retained
A/D converter Functioning Functioning Reset Reset
6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an
interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is
not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested interrupt is
disabled in the interrupt enable register. a transition is made to subactive mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.