Datasheet

Section 7 ROM
Rev. 2.00 Sep. 23, 2005 Page 83 of 444
REJ09B0068-0200
7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit Bit Name
Initial
Value R/W Description
7 to 5  All 0  Reserved
These bits are always read as 0.
4 EB4 0 R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
3 EB3 0 R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF
will be erased.
2 EB2 0 R/W When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF
will be erased.
1 EB1 0 R/W When this bit is set to 1, 1 kbyte of H'0400 to H'07FF
will be erased.
0 EB0 0 R/W When this bit is set to 1, 1 kbyte of H'0000 to H'03FF
will be erased.
7.2.4 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, and EBR1.
Bit Bit Name
Initial
Value R/W Description
7 FLSHE 0 R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers
cannot be accessed when this bit is set to 0.
6 to 0  All 0  Reserved
These bits are always read as 0.