Datasheet

Rev. 2.00 Sep. 23, 2005 Page x of xxx
3.2.4 Interrupt Enable Register 2 (IENR2)...................................................................... 49
3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 49
3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 51
3.2.7 Wakeup Interrupt Flag Register (IWPR)................................................................ 51
3.3 Reset Exception Handling.................................................................................................... 53
3.4 Interrupt Exception Handling .............................................................................................. 53
3.4.1 External Interrupts .................................................................................................. 53
3.4.2 Internal Interrupts ................................................................................................... 55
3.4.3 Interrupt Handling Sequence .................................................................................. 55
3.4.4 Interrupt Response Time......................................................................................... 56
3.5 Usage Notes......................................................................................................................... 58
3.5.1 Interrupts after Reset............................................................................................... 58
3.5.2 Notes on Stack Area Use ........................................................................................ 58
3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 58
Section 4 Address Break .....................................................................................59
4.1 Register Descriptions...........................................................................................................60
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 60
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 62
4.1.3 Break Address Registers (BARH, BARL).............................................................. 62
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 63
4.2 Operation ............................................................................................................................. 63
Section 5 Clock Pulse Generators .......................................................................65
5.1 System Clock Generator...................................................................................................... 65
5.1.1 Connecting Crystal Resonator ................................................................................ 66
5.1.2 Connecting Ceramic Resonator .............................................................................. 67
5.1.3 External Clock Input Method ................................................................................. 67
5.2 Prescalers............................................................................................................................. 68
5.2.1 Prescaler S .............................................................................................................. 68
5.3 Usage Notes......................................................................................................................... 68
5.3.1 Note on Resonators................................................................................................. 68
5.3.2 Notes on Board Design........................................................................................... 68
Section 6 Power-Down Modes............................................................................69
6.1 Register Descriptions...........................................................................................................69
6.1.1 System Control Register 1 (SYSCR1).................................................................... 70
6.1.2 System Control Register 2 (SYSCR2).................................................................... 72
6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 73
6.1.4 Module Standby Control Register 2 (MSTCR2) .................................................... 74