Datasheet

Rev. 2.00 Sep. 23, 2005 Page xi of xxx
6.2 Mode Transitions and States of LSI..................................................................................... 75
6.2.1 Sleep Mode .............................................................................................................76
6.2.2 Standby Mode.........................................................................................................77
6.2.3 Subsleep Mode........................................................................................................ 77
6.3 Operating Frequency in Active Mode.................................................................................. 78
6.4 Direct Transition.................................................................................................................. 78
6.5 Module Standby Function.................................................................................................... 78
Section 7 ROM ....................................................................................................79
7.1 Block Configuration.............................................................................................................80
7.2 Register Descriptions...........................................................................................................81
7.2.1 Flash Memory Control Register 1 (FLMCR1)........................................................ 81
7.2.2 Flash Memory Control Register 2 (FLMCR2)........................................................ 82
7.2.3 Erase Block Register 1 (EBR1) .............................................................................. 83
7.2.4 Flash Memory Enable Register (FENR)................................................................. 83
7.3 On-Board Programming Modes........................................................................................... 84
7.3.1 Boot Mode .............................................................................................................. 85
7.3.2 Programming/Erasing in User Program Mode........................................................ 87
7.4 Flash Memory Programming/Erasing..................................................................................88
7.4.1 Program/Program-Verify........................................................................................ 88
7.4.2 Erase/Erase-Verify.................................................................................................. 91
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory............................. 91
7.5 Program/Erase Protection .................................................................................................... 93
7.5.1 Hardware Protection ............................................................................................... 93
7.5.2 Software Protection................................................................................................. 93
7.5.3 Error Protection....................................................................................................... 93
7.6 Programmer Mode............................................................................................................... 94
Section 8 RAM ....................................................................................................95
Section 9 I/O Ports...............................................................................................97
9.1 Port 1.................................................................................................................................... 97
9.1.1 Port Mode Register 1 (PMR1)................................................................................ 98
9.1.2 Port Control Register 1 (PCR1) ..............................................................................99
9.1.3 Port Data Register 1 (PDR1)................................................................................... 99
9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 100
9.1.5 Pin Functions ........................................................................................................ 100
9.2 Port 2.................................................................................................................................. 103
9.2.1 Port Control Register 2 (PCR2) ............................................................................ 103
9.2.2 Port Data Register 2 (PDR2)................................................................................. 104