Datasheet

Rev. 2.00 Sep. 23, 2005 Page xiv of xxx
12.4.6 Reset Synchronous PWM Mode........................................................................... 193
12.4.7 Complementary PWM Mode................................................................................ 197
12.4.8 Buffer Operation................................................................................................... 208
12.4.9 Timer Z Output Timing ........................................................................................ 216
12.5 Interrupts............................................................................................................................ 218
12.5.1 Status Flag Set Timing.......................................................................................... 218
12.5.2 Status Flag Clearing Timing................................................................................. 220
12.6 Usage Notes....................................................................................................................... 220
Section 13 Watchdog Timer..............................................................................229
13.1 Features.............................................................................................................................. 229
13.2 Register Descriptions......................................................................................................... 230
13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 230
13.2.2 Timer Counter WD (TCWD)................................................................................ 231
13.2.3 Timer Mode Register WD (TMWD).................................................................... 232
13.3 Operation ........................................................................................................................... 233
Section 14 14-Bit PWM ....................................................................................235
14.1 Features.............................................................................................................................. 235
14.2 Input/Output Pin ................................................................................................................236
14.3 Register Descriptions......................................................................................................... 236
14.3.1 PWM Control Register (PWCR) .......................................................................... 236
14.3.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................. 237
14.4 Operation ........................................................................................................................... 237
Section 15 Serial Communication Interface 3 (SCI3).......................................239
15.1 Features.............................................................................................................................. 239
15.2 Input/Output Pins...............................................................................................................241
15.3 Register Descriptions......................................................................................................... 242
15.3.1 Receive Shift Register (RSR) ............................................................................... 242
15.3.2 Receive Data Register (RDR)............................................................................... 242
15.3.3 Transmit Shift Register (TSR).............................................................................. 242
15.3.4 Transmit Data Register (TDR).............................................................................. 243
15.3.5 Serial Mode Register (SMR) ................................................................................ 243
15.3.6 Serial Control Register 3 (SCR3) ......................................................................... 245
15.3.7 Serial Status Register (SSR) ................................................................................. 247
15.3.8 Bit Rate Register (BRR) ....................................................................................... 249
15.4 Operation in Asynchronous Mode..................................................................................... 256
15.4.1 Clock..................................................................................................................... 256
15.4.2 SCI3 Initialization................................................................................................. 257