Datasheet

Section 11 Timer V
TIM08V0A_000120030300 Rev. 2.00 Sep. 23, 2005 Page 133 of 444
REJ09B0068-0200
Section 11 Timer V
The timer V is an 8-bit timer based on an 8-bit counter. The timer V counts external events.
Compare-match signals with two registers can also be used to reset the counter, request an
interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a
trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger,
with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of the timer V.
11.1 Features
• Choice of seven clock signals
Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock.
• Selection of counter clear source
Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
• Control of timer output by combination of two compare match signals
Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
• Three interrupt sources: compare match A, compare match B, timer overflow
• Count start function by trigger input
Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.