Datasheet

Section 11 Timer V
Rev. 2.00 Sep. 23, 2005 Page 145 of 444
REJ09B0068-0200
N – 1 N H'00
φ
TMRIV
(External counter
reset input pin)
TCNTV reset
signal
TCNTV
Figure 11.8 Clear Timing by TMRIV Input
11.5 Timer V Application Examples
11.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set the CCLR1 and CCLR0 bits in TCRV0 so that TCNTV will be cleared by compare match
with TCORA.
2. Set the OS3 to OS0 bits in TCSRV so that the output will go to 1 at compare match with
TCORA and to 0 at compare match with TCORB.
3. Set the CKS2 to CKS0 bits in TCRV0 and the ICKS0 bit in TCRV1 to select the desired clock
source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
Counter cleared
Time
TCNTV value
H'FF
TCORA
TCORB
H'00
TMOV
Figure 11.9 Pulse Output Example