Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 152 of 444
REJ09B0068-0200
ITMZ0
FTIOD0
FTIOC0
FTIOB0
FTIOA0
TCNT_0
GRA_0 GRB_0
GRC_0 GRD_0
TCR_0
TIORA_0
TSR_0
TIORC_0
TIER_0
POCR_0
TCNT_0 :
TCR_0 :
GRA_0, GRB_0:
GRC_0, GRD_0 :
TIORA_0 :
TIORC_0 :
TSR_0 :
TIER_0 :
POCR_0 :
ITMZ0 :
Timer counter_0 (16 bits)
General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers:
16 bits × 4)
Timer control register_0 (8 bits)
Timer I/O control register A_0 (8 bits)
Timer I/O control register C_0 (8 bits)
Timer status register_0 (8 bits)
Timer interrupt enable register_0 (8 bits)
PWM mode output level control register_0 (8 bits)
Channel 0 interrupt
[Legend]
φ, φ/2,
φ/4, φ/8
Clock select
Control logic
Module data bus
Comparator
Figure 12.2 Timer Z (Channel 0) Block Diagram