Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 165 of 444
REJ09B0068-0200
12.3.9 Timer Control Register (TCR)
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Bit Bit Name
Initial
value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
000: Disables TCNT clearing
001: Clears TCNT by GRA compare match/input
capture*
1
010: Clears TCNT by GRB compare match/input
capture*
1
011: Synchronization clear; Clears TCNT in
synchronous
with counter clearing of the other channel's timer*
2
100: Disables TCNT clearing
101: Clears TCNT by GRC compare match/input
capture*
1
110: Clears TCNT by GRD compare match/input
capture*
1
111: Synchronization clear; Clears TCNT in
synchronous with counter clearing of the other
channel's timer*
2
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges