Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 168 of 444
REJ09B0068-0200
Bit Bit Name
Initial
value R/W Description
2
1
0
IOA2
IOA1
IOA0
0
0
0
R/W
R/W
R/W
I/O Control A2 to A0
GRA is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling
edges
Legend: X: Don't care