Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 185 of 444
REJ09B0068-0200
2. Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR. Figure 12.18 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least two system clock (φ) cycles.
TCNT
Input capture signal
Input capture input
GR
N
N
φ
Figure 12.18 Input Capture Signal Timing