Datasheet

Rev. 2.00 Sep. 23, 2005 Page xx of xxx
Figure 5.7 Example of Incorrect Board Design ............................................................................ 68
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 75
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration............................................................................ 80
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 87
Figure 7.3 Program/Program-Verify Flowchart ........................................................................... 89
Figure 7.4 Erase/Erase-Verify Flowchart ..................................................................................... 92
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration.............................................................................................. 97
Figure 9.2 Port 2 Pin Configuration............................................................................................ 103
Figure 9.3 Port 3 Pin Configuration............................................................................................ 107
Figure 9.4 Port 5 Pin Configuration............................................................................................ 110
Figure 9.5 Port 6 Pin Configuration............................................................................................ 116
Figure 9.6 Port 7 Pin Configuration............................................................................................ 122
Figure 9.7 Port 8 Pin Configuration............................................................................................ 125
Figure 9.8 Port B Pin Configuration...........................................................................................127
Section 10 Timer B1
Figure 10.1 Block Diagram of Timer B1.................................................................................... 129
Section 11 Timer V
Figure 11.1 Block Diagram of Timer V ..................................................................................... 134
Figure 11.2 Increment Timing with Internal Clock.................................................................... 143
Figure 11.3 Increment Timing with External Clock................................................................... 143
Figure 11.4 OVF Set Timing...................................................................................................... 143
Figure 11.5 CMFA and CMFB Set Timing ................................................................................ 144
Figure 11.6 TMOV Output Timing ............................................................................................ 144
Figure 11.7 Clear Timing by Compare Match............................................................................ 144
Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 145
Figure 11.9 Pulse Output Example............................................................................................. 145
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 146
Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 147
Figure 11.12 Contention between TCORA Write and Compare Match..................................... 148
Figure 11.13 Internal Clock Switching and TCNTV Operation................................................. 148
Section 12 Timer Z
Figure 12.1 Timer Z Block Diagram .......................................................................................... 151
Figure 12.2 Timer Z (Channel 0) Block Diagram ...................................................................... 152
Figure 12.3 Timer Z (Channel 1) Block Diagram ...................................................................... 153