Datasheet

Rev. 2.00 Sep. 23, 2005 Page xxi of xxx
Figure 12.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary
PWM Mode ............................................................................................................. 160
Figure 12.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))........ 174
Figure 12.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits)).............174
Figure 12.7 Example of Counter Operation Setting Procedure .................................................. 175
Figure 12.8 Free-Running Counter Operation ............................................................................ 176
Figure 12.9 Periodic Counter Operation..................................................................................... 177
Figure 12.10 Count Timing at Internal Clock Operation............................................................ 177
Figure 12.11 Count Timing at External Clock Operation (Both Edges Detected)...................... 178
Figure 12.12 Example of Setting Procedure for Waveform Output by Compare Match............ 179
Figure 12.13 Example of 0 Output/1 Output Operation ............................................................. 180
Figure 12.14 Example of Toggle Output Operation ................................................................... 181
Figure 12.15 Output Compare Timing........................................................................................182
Figure 12.16 Example of Input Capture Operation Setting Procedure ....................................... 183
Figure 12.17 Example of Input Capture Operation..................................................................... 184
Figure 12.18 Input Capture Signal Timing................................................................................. 185
Figure 12.19 Example of Synchronous Operation Setting Procedure ........................................ 186
Figure 12.20 Example of Synchronous Operation...................................................................... 187
Figure 12.21 Example of PWM Mode Setting Procedure .......................................................... 188
Figure 12.22 Example of PWM Mode Operation (1) ................................................................. 189
Figure 12.23 Example of PWM Mode Operation (2) ................................................................. 190
Figure 12.24 Example of PWM Mode Operation (3) ................................................................. 191
Figure 12.25 Example of PWM Mode Operation (4) ................................................................. 192
Figure 12.26 Example of Reset Synchronous PWM Mode Setting Procedure........................... 194
Figure 12.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ......195
Figure 12.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ......196
Figure 12.29 Example of Complementary PWM Mode Setting Procedure................................ 199
Figure 12.30 Canceling Procedure of Complementary PWM Mode.......................................... 200
Figure 12.31 Example of Complementary PWM Mode Operation (1)....................................... 201
Figure 12.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2)................................................................203
Figure 12.32 (2) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3)................................................................ 204
Figure 12.33 Timing of Overshooting ........................................................................................ 205
Figure 12.34 Timing of Undershooting ...................................................................................... 205
Figure 12.35 Compare Match Buffer Operation......................................................................... 208
Figure 12.36 Input Capture Buffer Operation............................................................................. 208
Figure 12.37 Example of Buffer Operation Setting Procedure................................................... 209
Figure 12.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register) ................................................. 210