Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 205 of 444
REJ09B0068-0200
In complementary PWM mode, when the counter switches from up-counter to down-counter or
vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the
conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual
settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings
are shown in figures 12.33 and 12.34.
GR
Buffer transfer signal
Set to 1
Flag is not set
Transferred
to buffer
Not transferred
to buffer
N + 1
GRA_0
TCNT
N
N - 1 N - 1N
N
IMFA
Figure 12.33 Timing of Overshooting
H'FFFFH'0001 H'0001H'0000H'0000
GR
UDF
TCNT
Buffer transfer signal
Set to 1
Flag is not set
Transferred
to buffer
Not transferred
to buffer
Figure 12.34 Timing of Undershooting
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for BR, BR is transferred to GR when the counter is incremented by compare match
A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits,