Datasheet

Rev. 2.00 Sep. 23, 2005 Page xxii of xxx
Figure 12.39 Example of Compare Match Timing for Buffer Operation ................................... 211
Figure 12.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register)...................................................... 212
Figure 12.41 Input Capture Timing of Buffer Operation............................................................ 213
Figure 12.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 214
Figure 12.43 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 215
Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 216
Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 216
Figure 12.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 217
Figure 12.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 217
Figure 12.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 218
Figure 12.49 IMF Flag Set Timing at Input Capture .................................................................. 219
Figure 12.50 OVF Flag Set Timing............................................................................................ 219
Figure 12.51 Status Flag Clearing Timing.................................................................................. 220
Figure 12.52 Contention between TCNT Write and Clear Operations....................................... 220
Figure 12.53 Contention between TCNT Write and Increment Operations ............................... 221
Figure 12.54 Contention between GR Write and Compare Match............................................. 221
Figure 12.55 Contention between TCNT Write and Overflow................................................... 222
Figure 12.56 Contention between GR Read and Input Capture.................................................. 223
Figure 12.57 Contention between Count Clearing and Increment Operations by Input
Capture .................................................................................................................. 224
Figure 12.58 Contention between GR Write and Input Capture................................................. 225
Figure 12.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the
Same Timing ......................................................................................................... 227
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer........................................................................ 229
Figure 13.2 Watchdog Timer Operation Example...................................................................... 233
Section 14 14-Bit PWM
Figure 14.1 Block Diagram of 14-Bit PWM .............................................................................. 235
Figure 14.2 Waveform Output by 14-Bit PWM ......................................................................... 238
Section 15 Serial Communication Interface 3 (SCI3)
Figure 15.1 Block Diagram of SCI3........................................................................................... 241
Figure 15.2 Data Format in Asynchronous Communication ...................................................... 256
Figure 15.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits).............. 256
Figure 15.4 Sample SCI3 Initialization Flowchart ..................................................................... 257