Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 212 of 444
REJ09B0068-0200
Figure 12.40 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TCNT, and falling edges have been selected
as the FIOCB pin input capture input edge. And both rising and falling edges have been selected
as the FIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in GRA upon the occurrence of
input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 12.41.
H'0180
H'0160
H'0005
H'0000
FTIOB
FTIOA
H'0160
H'0005
H'0005
GRA
H'0160
GRC
H'0180
GRB
TCNT value
Counter is cleared by the input capture B
Time
Input capture A
Figure 12.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register)