Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 216 of 444
REJ09B0068-0200
12.4.9 Timer Z Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR
and the external level.
1. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to
1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port
beforehand, any value can be output. Figure 12.44 shows the timing to enable or disable the
output of timer Z by TOER.
T1 T2
TOER
Address bus
TOER address
Timer Z
output pin
Timer Z output
I/O port
I/O port
Timer output
φ
Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER
2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4
input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the
output of timer Z will be disabled.
WKP4
TOER
Timer Z
output pin
Timer Z output
I/O port
Timer Z output I/O port
N H'FF
φ
Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger