Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 221 of 444
REJ09B0068-0200
2. Contention between TCNT Write and Increment Operations: If incrementation is done in T
2
state of a TCNT write cycle, TCNT writing has priority. Figure 12.53 shows the timing in this
case.
T 1 T 2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
TCNT input clock
TCNT write data
N
M
φ
Figure 12.53 Contention between TCNT Write and Increment Operations
3. Contention between GR Write and Compare Match: If a compare match occurs in the T
2
state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
12.54 shows the timing in this case.
T 1 T 2
GR N
M
TCNT
GR write cycle
GR address
WGR
(internal write signal)
GR write data
Compare match
signal
Disabled
N N+1
φ
Figure 12.54 Contention between GR Write and Compare Match