Datasheet

Section 12 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 225 of 444
REJ09B0068-0200
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T
2
state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 12.58 shows the timing in this case.
T 1 T 2
TCNT N
GR write cycle
GR address
Input capture
signal
WGR
(internal write signal)
Address bus
GR write data
GR
M
φ
Figure 12.58 Contention between GR Write and Input Capture
8. Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
A. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
B. Changing the settings of reset synchronous PWM mode to complementary PWM mode or
vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode
after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.