Datasheet

Rev. 2.00 Sep. 23, 2005 Page xxiv of xxx
Figure 16.18 Sample Flowchart for Master Receive Mode ........................................................ 310
Figure 16.19 Sample Flowchart for Slave Transmit Mode......................................................... 311
Figure 16.20 Sample Flowchart for Slave Receive Mode .......................................................... 312
Figure 16.21 Timing of Bit Synchronous Circuit ....................................................................... 314
Section 17 A/D Converter
Figure 17.1 Block Diagram of A/D Converter ........................................................................... 290
Figure 17.2 A/D Conversion Timing.......................................................................................... 296
Figure 17.3 External Trigger Input Timing ................................................................................ 297
Figure 17.4 A/D Conversion Accuracy Definitions (1).............................................................. 299
Figure 17.5 A/D Conversion Accuracy Definitions (2).............................................................. 300
Figure 17.6 Analog Input Circuit Example ................................................................................ 301
Section 18 Power-On Reset and Low-Voltage Detection Circuits
Figure 18.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 332
Figure 18.2 Operational Timing of Power-On Reset Circuit...................................................... 336
Figure 18.3 Operational Timing of LVDR Circuit ..................................................................... 337
Figure 18.4 Operational Timing of LVDI Circuit ...................................................................... 338
Figure 18.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 339
Section 19 Power Supply Circuit
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 341
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is not Used .............. 342
Section 21 Electrical Characteristics
Figure 21.1 System Clock Input Timing .................................................................................... 377
Figure 21.2 RES Low Width Timing.......................................................................................... 377
Figure 21.3 Input Timing............................................................................................................ 377
Figure 21.4 I
2
C Bus Interface Input/Output Timing ................................................................... 378
Figure 21.5 SCK3 Input Clock Timing ...................................................................................... 378
Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode...................................... 379
Figure 21.7 Output Load Circuit ................................................................................................ 379
Appendix
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 411
Figure B.2 Port 1 Block Diagram (P16, P14) ............................................................................. 412
Figure B.3 Port 1 Block Diagram (P15) ..................................................................................... 413
Figure B.4 Port 1 Block Diagram (P12, P10) ............................................................................. 414
Figure B.5 Port 1 Block Diagram (P11) ..................................................................................... 415
Figure B.6 Port 2 Block Diagram (P24, P23) ............................................................................. 416
Figure B.7 Port 2 Block Diagram (P22) ..................................................................................... 417
Figure B.8 Port 2 Block Diagram (P21) ..................................................................................... 418
Figure B.9 Port 2 Block Diagram (P20) ..................................................................................... 419