Datasheet

Section 13 Watchdog Timer
Rev. 2.00 Sep. 23, 2005 Page 231 of 444
REJ09B0068-0200
Bit Bit Name
Initial
Value R/W Description
2 WDON 1 R/W Watchdog Timer On
The TCWD starts counting up when the WDON bit is
set to 1 and halts when the WDON bit is cleared to 0.
The WDT is set enabled by default. To disable the
WDT, clear this bit to 0.
[Clearing conditions]
• When writing 0 to the B2WI bit and 0 to the WDON
bit while the TCSRWE bit =1.
[Setting condition]
• Reset
• When writing 1 to the B2WI bit and 0 to the WDON
bit while the TCSRWE bit =1.
1 B0WI 1 R/W Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read
as 1.
0 WRST 0 R/W Watchdog Timer Reset
[Setting condition]
• When TCWD overflows and an internal reset signal
is generated
[Clearing conditions]
• Reset by RES pin
• When writing 0 to the B2WI bit and 0 to the WDON
bit while the TCSRWE bit =1.
13.2.2 Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.