Datasheet

Section 15 Serial Communication Interface 3 (SCI3)
Rev. 2.00 Sep. 23, 2005 Page 241 of 444
REJ09B0068-0200
Clock
TXD
RXD
SCK3
BRR
SMR
SCR3
SSR
TDR
RDR
TSR
RSR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (φ/64, φ/16, φ/4, φ)
External
clock
BRC
Baud rate generator
Figure 15.1 Block Diagram of SCI3
15.2 Input/Output Pins
Table 15.2 shows the SCI3 pin configuration.
Table 15.2 Pin Configuration
Pin Name Abbreviation I/O Function
SCI3 clock SCK3 I/O SCI3 clock input/output
SCI3 receive data input RXD Input SCI3 receive data input
SCI3 transmit data output TXD Output SCI3 transmit data output