Datasheet

Section 15 Serial Communication Interface 3 (SCI3)
Rev. 2.00 Sep. 23, 2005 Page 245 of 444
REJ09B0068-0200
15.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, see section 15.7,
Interrupts.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5 TE 0 R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1,
this bit is automatically cleared and normal reception is
resumed. For details, see section 15.6, Multiprocessor
Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled.