Datasheet

Section 15 Serial Communication Interface 3 (SCI3)
Rev. 2.00 Sep. 23, 2005 Page 249 of 444
REJ09B0068-0200
15.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 15.3
shows the relationship between the N setting in BRR and the n setting in the CKS1 and CKS0 bits
of SMR in asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 15.3 and 15.4 are values in active (high-
speed) mode. Table 15.5 shows the relationship between the N setting in BRR and the n setting in
the CKS1 and CKS0 bits of SMR in clocked synchronous mode. The values shown in table 15.5
are values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N =
φ
64 × 2
2n–1
× B
× 10
6
– 1
Error (%) = – 1 × 100






φ × 10
6
(N + 1) × B × 64 × 2
2n–1
[Clocked Synchronous Mode]
N =
φ
8 × 2
2n–1
× B
× 10
6
– 1
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)