Datasheet

Section 20 List of Registers
Rev. 2.00 Sep. 23, 2005 Page 357 of 444
REJ09B0068-0200
Register
Name Reset Active Sleep Subsleep Standby Module
SMR Initialized   Initialized Initialized SCI3
BRR Initialized   Initialized Initialized
SCR3 Initialized   Initialized Initialized
TDR Initialized   Initialized Initialized
SSR Initialized   Initialized Initialized
RDR Initialized   Initialized Initialized
ADDRA Initialized   Initialized Initialized A/D converter
ADDRB Initialized   Initialized Initialized
ADDRC Initialized   Initialized Initialized
ADDRD Initialized   Initialized Initialized
ADCSR Initialized   Initialized Initialized
ADCR Initialized   Initialized Initialized
PWDRL Initialized     14-bit PWM
PWDRU Initialized    
PWCR Initialized    
TCSRWD Initialized     WDT*
TCWD Initialized    
TMWD Initialized    
ABRKCR Initialized     Address break
ABRKSR Initialized    
BARH Initialized    
BARL Initialized    
BDRH Initialized    
BDRL Initialized    
PUCR1 Initialized     I/O port
PUCR5 Initialized    
PDR1 Initialized    
PDR2 Initialized    
PDR3 Initialized    
PDR5 Initialized    
PDR6 Initialized    