Datasheet

Section 21 Electrical Characteristics
Rev. 2.00 Sep. 23, 2005 Page 377 of 444
REJ09B0068-0200
21.3 Operation Timing
t
OSC
V
IH
V
IL
t
CPH
t
CPL
t
CPr
OSC1
t
CPf
Figure 21.1 System Clock Input Timing
t
REL
V
IL
RES
t
REL
V
IL
V
CC
× 0.7
V
CC
OSC1
Figure 21.2 RES Low Width Timing
V
IH
V
IL
t
IL
NMI, TMIB1
IRQ0 to IRQ3
WKP0 to WKP5
ADTRG
FTIOA0 to FTIOD0,
FTIOA1 to FTIOD1,
TMCIV, TMRIV
TRGV
t
IH
Figure 21.3 Input Timing