Datasheet

Appendix
Rev. 2.00 Sep. 23, 2005 Page 400 of 444
REJ09B0068-0200
Table A.3 Number of Cycles in Each Instruction
Execution Status
Access Location
(Instruction Cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch S
I
2 —
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 or 3*
Word data access S
M
2 or 3*
Internal operation S
N
1
Note: * Depends on which on-chip peripheral module is accessed. For details, see section
20.1, Register Addresses (Address Order).