Datasheet

Rev. 2.00 Sep. 23, 2005 Page 437 of 354
REJ09B0068-0200
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details)
Preface vii When using the on-chip emulator (E7, E8) for H8/36064
program development and debugging, the following
restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be
used.
3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not
available to the user.
5. When the E7 or E8 is used, address breaks can be set as
either available to the user or for use by the E7 or E8. If
address breaks are set as being used by the E7 or E8, the
address break control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin
(open-drain in output mode).
Note has been deleted.
Section 7 ROM 79 The features of the 32-kbyte (4 kbytes are used for E7 or E8
control program area) flash memory built into the flash
memory (F-ZTAT) version are summarized below.
Section 8 RAM 95 Note: * When the E7 or E8 is used, area H'F780 to H'FB7F
must not be accessed.
Bit Bit Name
Description
0 SYNC Timer Synchronization
0: TCNT_1 and TCNT_0 operate as a different
timer
1: TCNT_1 and TCNT_0 are synchronized
TCNT_1 and TCNT_0 can be pre-set or
cleared synchronously
Section 12 Timer Z
12.3.2 Timer Mode
Register (TMDR)
157
12.4.4 Synchronous
Operation
187
Figure 12.20 shows an example of synchronous operation. In
this example, synchronous operation has been selected,
FTIOB0 and FTIOB1 have been designated for PWM mode,
GRA_0 compare match has been set as the channel 0
counter clearing source, and synchronous clearing has been
set for the channel 1 counter clearing source. In addition, the
same input clock has been set as the counter input clock for
channel 0 and channel 1. Two-phase PWM waveforms are
output from pins FTIOB0 and FTIOB1.