Datasheet

Rev. 2.00 Sep. 23, 2005 Page 438 of 354
REJ09B0068-0200
Item Page Revision (See Manual for Details)
12.4.9 Timer Z Output
Timing
Figure 12.44 Example of
Output Disable Timing of
Timer Z by Writing to
TOER
216
φ
Timer Z
output pin
Timer output
Address bus TOER address
T
1 T 2
I/O port
Timer Z output
I/O port
Figure 12.45 Example of
Output Disable Timing of
Timer Z by External Trigger
216
φ
TOER N
Timer Z
output pin
Timer Z output
Timer Z output
I/O port
I/O port
H'FF
Bit Bit Name Description
4 TCSRWE Timer Control/Status Register WD Write Enable
2 WDON Watchdog Timer On
The TCWD starts counting up when the WDON
bit is set to 1 and halts when the WDON bit is
cleared to 0. The WDT is set enabled by default.
To disable the WDT, clear this bit to 0.
[Clearing conditions]
• When writing 0 to the B2WI bit and 0 to the
WDON bit while the TCSRWE bit =1.
[Setting condition]
• Reset
• When writing 1 to the B2WI bit and 0 to the
WDON bit while the TCSRWE bit =1.
13.2.1 Timer Control/Status
Register WD (TCSRWD)
230,
231
13.3 Operation 233 Swapped with new one.