Datasheet

Section 3 Exception Handling
Rev. 2.00 Sep. 23, 2005 Page 44 of 444
REJ09B0068-0200
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Relative Module Exception Sources
Vector
Number Vector Address Priority
RES pin
Watchdog timer
Reset 0 H'0000, H'0001 High
 Reserved for system use 1 to 6 H'0002 to H'000D
External interrupt pin NMI 7 H'000E, H'000F
CPU Trap instruction (#0) 8 H'0010, H'0011
Trap instruction (#1) 9 H'0012, H'0013
Trap instruction (#2) 10 H'0014, H'0015
Trap instruction (#3) 11 H'0016, H'0017
Address break Break conditions satisfied 12 H'0018, H'0019
CPU Direct transition by executing
the SLEEP instruction
13 H'001A, H'001B
External interrupt pin IRQ0
Low-voltage detection interrupt
14 H'001C, H'001D
IRQ1 15 H'001E, H'001F
IRQ2 16 H'0020, H'0021
IRQ3 17 H'0022, H'0023
WKP 18 H'0024, H'0025
19 H'0026, H'0027  Reserved for system use
20 H'0028, H'0029
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
22 H'002C, H'002D
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23 H'002E, H'002F
Low