Datasheet

Section 3 Exception Handling
Rev. 2.00 Sep. 23, 2005 Page 45 of 444
REJ09B0068-0200
Relative Module Exception Sources
Vector
Number Vector Address Priority
IIC2 Transmit data empty
Transmit end
Receive data full
Arbitration lost/Overrun error
NACK detection
Stop condition detection
24 H'0030, H'0031 High
A/D converter A/D conversion end 25 H'0032, H'0033
Timer Z Compare match/input capture
A0 to D0
Timer Z overflow
26 H'0034, H'0035
Compare match/input capture
A1 to D1
Timer Z overflow
Timer Z underflow
27 H'0036, H'0037
Timer B1 Timer B1 overflow 29 H'003A, H'003B
SCI3_2 Receive data full
Transmit data empty
Transmit end
Receive error
32 H'0040, H'0041
Low
3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)
• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt flag register 1 (IRR1)
• Interrupt flag register 2 (IRR2)
• Wakeup interrupt flag register (IWPR)