Datasheet

Section 3 Exception Handling
Rev. 2.00 Sep. 23, 2005 Page 49 of 444
REJ09B0068-0200
3.2.4 Interrupt Enable Register 2 (IENR2)
IENR2 enables, timer B1 overflow interrupts.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 0  Reserved
These bits are always read as 0.
5 IENTB1 0 R/W Timer B1 Interrupt Enable
When this bit is set to 1, timer B1 overflow interrupt
requests are enabled.
4 to 0  All 1  Reserved
These bits are always read as 1.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
3.2.5 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts and IRQ3 to IRQ0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6  0  Reserved
This bit is always read as 0.
5, 4  All 1  Reserved
These bits are always read as 1.