Datasheet

Section 3 Exception Handling
Rev. 2.00 Sep. 23, 2005 Page 53 of 444
REJ09B0068-0200
3.3 Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. The reset
exception handling sequence is shown in figure 3.1. For details, refer to section 18, Power-On
Reset and Low-Voltage Detection Circuits.
The reset exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.
(1) NMI Interrupt
NMI interrupt is requested by input signal edge to the NMI pin. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of the NMIEG bit in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit
value in CCR.
(2) IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to the IRQ3 to IRQ0 pins. These four
interrupts are given different vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of the IEG3 to IEG0 bits in IEGR1.
When the IRQ3 to IRQ0 pins are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting the IEN3 to IEN0 bits in IENR1.