Datasheet

Section 3 Exception Handling
Rev. 2.00 Sep. 23, 2005 Page 54 of 444
REJ09B0068-0200
(3) WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to the WKP5 to WKP0 pins. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of the WPEG5 to WPEG0 bits in
IEGR2.
When the WKP5 to WKP0 pins are designated for interrupt input in PMR5 and the designated
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt.
These interrupts can be masked by setting the IENWP bit in IENR1.
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
RES
Internal
processing
Initial program
instruction prefetch
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(2) (3)
(2)(1)
Reset cleared
Figure 3.1 Reset Sequence