Datasheet

Section 4 Address Break
Rev. 2.00 Sep. 23, 2005 Page 62 of 444
REJ09B0068-0200
4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit Bit Name
Initial
Value R/W Description
7 ABIF 0 R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF = 1 is read
6 ABIE 0 R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5 to 0  All 1  Reserved
These bits are always read as 1.
4.1.3 Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit readable/writable registers that set the address for generating an
address break interrupt. When setting the address break condition to the instruction execution
cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF.