Datasheet

Section 5 Clock Pulse Generator
Rev. 3.00 Sep. 10, 2007 Page 75 of 528
REJ09B0216-0300
Bit Bit Name
Initial
Value
R/W Description
4
TRMDRWE 0 R/W Trimming Data Register Write Enable
This register can be written to when the LOCKDW bit is 0
and this bit is 1.
[Setting condition]
• When writing 0 to the WRI bit while writing 1 to the
TRMDRWE bit while the PRWE bit is 1
[Clearing conditions]
• Reset
• When writing 0 to the WRI bit and writing 0 to the
TRMDRWE bit while the PRWE bit is 1
3 to 0  All 1  Reserved
These bits are always read as 1.
5.2.3 RC Trimming Data Register (RCTRMDR)
RCTRMDR stores the trimming data of the on-chip oscillator frequency (FSEL = 1, 20 MHz).
Bit Bit Name
Initial
Value
R/W Description
7 TRMD7 (0)* R/W
6 TRMD6 (0)* R/W
5 TRMD5 (0)* R/W
4 TRMD4 (0)* R/W
3 TRMD3 (0)* R/W
2 TRMD2 (0)* R/W
1 TRMD1 (0)* R/W
0 TRMD0 (0)* R/W
Trimming Data (FSEL = 1, 20 MHz)
The trimming data is loaded from the flash memory to this
register right after a reset.
The on-chip oscillator clock (FSEL = 1, 20 MHz) can be
trimmed by changing these bits.
The frequency of the on-chip oscillator clock changes
right after writing these bits. These bits are initialized to
H'00.
Changes in frequency are shown below (bit TRMD7 is a
sign bit).
(Min.) H'80 ← … ← H'FF ← … ← H'00 → … →H'01 → …
→ H'7F (Max.)
Note: * These values are initialized to the trimming data loaded from the flash memory.