Datasheet

Section 5 Clock Pulse Generator
Rev. 3.00 Sep. 10, 2007 Page 85 of 528
REJ09B0216-0300
T
chk
[Legend]
φOSC: External clock
φRC: On-chip oscillator clock
φ: System clock
OSCHLT: Bit 1 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
CKSWIF: Bit 2 in CKCSR
φ halt*
2
On-chip oscillator
clock operation
Notes: 1. 44 × φ
RC
≤ T
chk
≤ 48 × φ
RC
2. The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φ
RC
clock.
φOSC
φRC
PHISTOP
(Internal signal)
φ
OSCHLT
CKSTA
External clock operation
CKSWIF
External clock halt
φ
OSC
halt
detected*
1
Figure 5.8 External Oscillation Backup Timing