Datasheet

Section 9 I/O Ports
Rev. 3.00 Sep. 10, 2007 Page 138 of 528
REJ09B0216-0300
9.2.2 Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Bit Bit Name
Initial
Value
R/W Description
7 to 5  All 1  Reserved
These bits are always read as 1.
4
3
2
1
0
P24
P23
P22
P21
P20
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
PDR2 stores output data for port 2 pins.
If PDR2 is read while PCR2 bits are set to 1, the value
stored in PDR2 is read. If PDR2 is read while PCR2 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR2.
9.2.3 Port Mode Register 3 (PMR3)
PMR3 selects the CMOS output or NMOS open-drain output for port 2.
Bit Bit Name
Initial
Value
R/W Description
7 to 5  All 0  Reserved
These bits are always read as 0.
4
3
POF24
POF23
0
0
R/W
R/W
When the bit is set to 1, the corresponding pin is cut off
by PMOS and it functions as the NMOS open-drain
output. When cleared to 0, the pin functions as the CMOS
output.
2 to 0  All 1  Reserved
These bits are always read as 1.