Datasheet

Section 21 List of Registers
Rev. 3.00 Sep. 10, 2007 Page 396 of 528
REJ09B0216-0300
21.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Register
Abbre-
viation Bit No Address
Module
Name
Data
Bus
Width
Access
State
   H'F000
to
H'F6FF
  
Timer control register_0 TCR_0 8 H'F700 Timer Z 8 2
Timer I/O control register A_0 TIORA_0 8 H'F701 Timer Z 8 2
Timer I/O control register C_0 TIORC_0 8 H'F702 Timer Z 8 2
Timer status register_0 TSR_0 8 H'F703 Timer Z 8 2
Timer interrupt enable register_0 TIER_0 8 H'F704 Timer Z 8 2
PWM mode output level control
register_0
POCR_0 8 H'F705 Timer Z 8 2
Timer counter_0 TCNT_0 16 H'F706 Timer Z 16 2
General register A_0 GRA_0 16 H'F708 Timer Z 16 2
General register B_0 GRB_0 16 H'F70A Timer Z 16 2
General register C_0 GRC_0 16 H'F70C Timer Z 16 2
General register D_0 GRD_0 16 H'F70E Timer Z 16 2
Timer control register_1 TCR_1 8 H'F710 Timer Z 8 2
Timer I/O control register A_1 TIORA_1 8 H'F711 Timer Z 8 2
Timer I/O control register C_1 TIORC_1 8 H'F712 Timer Z 8 2
Timer status register_1 TSR_1 8 H'F713 Timer Z 8 2
Timer interrupt enable register_1 TIER_1 8 H'F714 Timer Z 8 2
PWM mode output level control
register_1
POCR_1 8 H'F715 Timer Z 8 2
Timer counter_1 TCNT_1 16 H'F716 Timer Z 16 2
General register A_1 GRA_1 16 H'F718 Timer Z 16 2
General register B_1 GRB_1 16 H'F71A Timer Z 16 2