Datasheet

Section 5 Clock Pulse Generator
Rev. 3.00 Sep. 10, 2007 Page 83 of 528
REJ09B0216-0300
5.3.2 Clock Switching Timing
The timing for switching clocks are shown in figures 5.6 to 5.8.
[Legend]
φOSC: External clock
φRC: On-chip oscillator clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
Wait for external
oscillation settling
φ halt*
External clock operation
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the first
rising edge of the φ
OSC
clock after seven clock cycles of the φ
RC
clock have elapsed.
φOSC
Nwait
φRC
PHISTOP
(Internal signal)
φ
OSCSEL
CKSTA
On-chip oscillator clock operation
Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock