Datasheet

Rev. 3.00 Sep. 10, 2007 Page xxiii of xxxii
Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ...........................................................................................167
Figure 10.2 Definition of Time Expression ................................................................................173
Figure 10.3 Initial Setting Procedure..........................................................................................176
Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 177
Section 11 Timer B1
Figure 11.1 Block Diagram of Timer B1.................................................................................... 179
Section 12 Timer V
Figure 12.1 Block Diagram of Timer V...................................................................................... 186
Figure 12.2 Increment Timing with Internal Clock .................................................................... 193
Figure 12.3 Increment Timing with External Clock ................................................................... 193
Figure 12.4 OVF Set Timing ......................................................................................................193
Figure 12.5 CMFA and CMFB Set Timing ................................................................................ 194
Figure 12.6 TMOV Output Timing ............................................................................................194
Figure 12.7 Clear Timing by Compare Match............................................................................ 194
Figure 12.8 Clear Timing by TMRIV Input ...............................................................................195
Figure 12.9 Pulse Output Example ............................................................................................. 195
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input....................................... 196
Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 197
Figure 12.12 Contention between TCORA Write and Compare Match ..................................... 198
Figure 12.13 Internal Clock Switching and TCNTV Operation .................................................198
Section 13 Timer Z
Figure 13.1 Timer Z Block Diagram .......................................................................................... 201
Figure 13.2 Timer Z (Channel 0) Block Diagram ......................................................................202
Figure 13.3 Timer Z (Channel 1) Block Diagram ......................................................................203
Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode and
Complementary PWM Mode.................................................................................. 210
Figure 13.5 Accessing Operation of 16-Bit Register
(between CPU and TCNT (16 bits)) .......................................................................222
Figure 13.6 Accessing Operation of 8-Bit Register
(between CPU and TSTR (8 bits)).......................................................................... 222
Figure 13.7 Example of Counter Operation Setting Procedure .................................................. 223
Figure 13.8 Free-Running Counter Operation ............................................................................224
Figure 13.9 Periodic Counter Operation.....................................................................................225
Figure 13.10 Count Timing at Internal Clock Operation............................................................ 225
Figure 13.11 Count Timing at External Clock Operation (Both Edges Detected)...................... 226
Figure 13.12 Example of Setting Procedure for Waveform Output
by Compare Match................................................................................................ 227
Figure 13.13 Example of 0 Output/1 Output Operation .............................................................228