Datasheet

Section 13 Timer Z
Rev. 3.00 Sep. 10, 2007 Page 269 of 528
REJ09B0216-0300
T1 T2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
TCNT input clock
TCNT write data
N
M
φ
Figure 13.53 Contention between TCNT Write and Increment Operations
3. Contention between GR Write and Compare Match: If a compare match occurs in the T
2
state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
13.54 shows the timing in this case.
T 1 T 2
GR N M
TCNT
GR write cycle
GR address
WGR
(internal write signal)
GR write data
Compare match
signal
Disabled
N N+1
φ
Figure 13.54 Contention between GR Write and Compare Match