Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 64 (14x14) 16-Bit 16 MHz I/O number 47

Section 17 I

2

C Bus Interface 2 (IIC2)

Rev. 3.00 Sep. 10, 2007 Page 330 of 528

REJ09B0216-0300

SCL

ICCR1

Transfer clock

generation

circuit

Address

comparator

Interrupt

generator

Interrupt request

Bus state

decision circuit

Arbitration

decision circuit

Noise canceler

Noise canceler

Output

control

Output

control

Transmission/

reception

control circuit

ICCR2

ICMR

ICSR

ICIER

ICDRR

ICDRS

ICDRT

I

2

C bus control register 1

I

2

C bus control register 2

I

2

C bus mode register

I

2

C bus status register

I

2

C bus interrupt enable register

I

2

C bus transmit data register

I

2

C bus receive data register

I

2

C bus shift register

Slave address register

[Legend]

ICCR1:

ICCR2:

ICMR:

ICSR:

ICIER:

ICDRT:

ICDRR:

ICDRS:

SAR:

SAR

SDA

Internal data bus

Figure 17.1 Block Diagram of I

2

C Bus Interface 2