Datasheet

Appendix
Rev. 3.00 Sep. 10, 2007 Page 478 of 528
REJ09B0216-0300
Table A.3 Number of Cycles in Each Instruction
Access Location
Execution Status
(Instruction Cycle)
On-Chip Memory On-Chip Peripheral Module
Instruction fetch S
I
2 —
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 or 3*
Word data access S
M
2 or 3*
Internal operation S
N
1
Note: * Depends on which on-chip peripheral module is accessed. See section 21.1, Register
Addresses (Address Order).