Datasheet
Section 3 Exception Handling
Rev. 3.00 Sep. 10, 2007 Page 57 of 528
REJ09B0216-0300
RES
φ
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(16 bits)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(2)
(1)
(3)
(2)
Reset cleared
Reset cleared
Vector fetch
Initial program
instruction
prefetch
Internal
processing
RES
φ
Internal address bus
Normal mode operation
Advanced mode operation
Internal read signal
Internal write signal
Internal data bus
(16 bits)
(1), (3) Reset exception handling vector address ((1) = H'000000 (3) = H'000002)
(2), (4) Start address (contents of reset exception handling vector address)
(5) Start address
(6) Initial program instruction
(2) (4) (6)
(1) (3) (5)
Vector fetch
Initial program
instruction
prefetch
Internal
processing
Figure 3.1 Reset Sequence










